About: Clock gating

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Technique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states)

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  • technique used in synchronous circuits for reducing dynamic power dissipation, by adding more logic to a circuit to prune the clock tree (disabling portions of the circuitry so that the flip-flops in them do not have to switch states) (en)
  • tekniko por redukti procesoran pov-konsumon per dinamika malŝaltado de partoj de la cirkvito (eo)
  • Methode bei elektronischen synchronen Digitalschaltungen (de)
  • tècnica utilitzada en circuits síncrons per reduir la dissipació de potència dinàmica, afegint més lògica a un circuit per podar l'arbre del rellotge (desactivant parts dels circuits perquè els flip-flops en ells no hagin de canviar d'estat) (ca)
  • קטימת שעון (iw)
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  • Clock gating (en)
  • Clock-Gating (de)
  • Clock gating (fr)
  • Clock gating (it)
  • 클럭 게이팅 (ko)
  • Clock gating (uk)
  • Clock gating (ru)
  • 时钟门控 (zh)
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