About: Electronic design automation

An Entity of Type: Concept, from Named Graph: http://dbpedia.org, within Data Space: dbpedia.org

Property	Value
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rdfs:label	Electronic design automation (en)
skos:broader	dbc:Digital_electronics dbc:Electronic_design
skos:prefLabel	Electronic design automation (en)
prov:wasDerivedFrom	wikipedia-en:Category:Electronic_design_automation?oldid=952507623&ns=14
is dbo:wikiPageWikiLink of	dbr:Programmable_Array_Logic dbr:Schematic dbr:Electromagnetic_field_solver dbr:Electromigration dbr:Electronic_circuit_simulation dbr:Electronic_design_automation dbr:Electronic_system-level_design_and_verification dbr:Engineering_change_order dbr:Network_on_a_chip dbr:Symbolic_simulation dbr:Design_closure dbr:Design_flow_(EDA) dbr:Algorithmic_state_machine dbr:Antenna_effect dbr:Ultra-large-scale_systems dbr:Design_for_additive_manufacturing dbr:Design_for_manufacturability dbr:Design_for_testing dbr:EDA_database dbr:Input/output_Buffer_Information_Specification dbr:Integrated_circuit_layout dbr:Potential_applications_of_carbon_nanotubes dbr:And-inverter_graph dbr:Elmore_delay dbr:Generic_array_logic dbr:Low-power_FSM_synthesis dbr:Netlist dbr:Noise_margin dbr:Silicon_compiler dbr:Ladder_logic dbr:Open_Verification_Methodology dbr:Logic_optimization dbr:Silvaco_Data_Systems_v._Intel_Corp. dbr:Clock_gating dbr:Fault_coverage dbr:Feedback-controlled_electromigration dbr:Hardware_obfuscation dbr:Hardware_watermarking dbr:Physical_design_(electronics) dbr:Programmable_logic_array dbr:Standard_cell dbr:Transaction-level_modeling dbr:Maze_runner dbr:Data_processing_unit dbr:Dolphin_Integration dbr:Gajski–Kuhn_chart dbr:Logic_simulation dbr:Logic_synthesis dbr:Power_optimization_(EDA) dbr:Cell_(EDA) dbr:Central_processing_unit dbr:Digital_electronics dbr:Floorplan_(microelectronics) dbr:Graphical_system_design dbr:Graphics_processing_unit dbr:Lee_algorithm dbr:Semiconductor_intellectual_property_core dbr:Power_gating dbr:Register-transfer_level dbr:High-level_synthesis dbr:Asynchronous_system dbr:Black's_equation dbr:High-level_verification dbr:Touchstone_file dbr:Boolean_satisfiability_problem dbr:Planar_SAT dbr:Circuit_extraction dbr:Fiduccia–Mattheyses_algorithm dbr:Semiconductor_process_simulation dbr:Schematic_capture dbr:Mask_data_preparation dbr:Multi-project_wafer_service dbr:Satisfiability_modulo_theories dbr:SCALD dbr:Signal_integrity dbr:Universal_Verification_Methodology dbr:VISC_architecture dbr:IC_layout_editor dbr:IEC_61131-3 dbr:Placement_(electronic_design_automation) dbr:Platform-based_design dbr:Rent's_rule dbr:Test_compression dbr:Simulation_software dbr:PBIST dbr:Place_and_route dbr:Multi-channel_length dbr:Stuck-at_fault dbr:Semiconductor_device_modeling dbr:Substrate_coupling dbr:Signoff_(electronic_design_automation) dbr:Resolution_enhancement_technologies dbr:Power_network_design_(IC) dbr:Schematic_editor dbr:Systems_design dbr:Technology_CAD
is dcterms:subject of	dbr:Programmable_Array_Logic dbr:Schematic dbr:Electromagnetic_field_solver dbr:Electromigration dbr:Electronic_circuit_simulation dbr:Electronic_design_automation dbr:Electronic_system-level_design_and_verification dbr:Engineering_change_order dbr:Network_on_a_chip dbr:Symbolic_simulation dbr:Design_closure dbr:Design_flow_(EDA) dbr:Algorithmic_state_machine dbr:Antenna_effect dbr:Ultra-large-scale_systems dbr:Design_for_additive_manufacturing dbr:Design_for_manufacturability dbr:Design_for_testing dbr:EDA_database dbr:Input/output_Buffer_Information_Specification dbr:Integrated_circuit_layout dbr:Potential_applications_of_carbon_nanotubes dbr:And-inverter_graph dbr:Elmore_delay dbr:Generic_array_logic dbr:Low-power_FSM_synthesis dbr:Netlist dbr:Noise_margin dbr:Silicon_compiler dbr:Ladder_logic dbr:Open_Verification_Methodology dbr:Logic_optimization dbr:Silvaco_Data_Systems_v._Intel_Corp. dbr:Clock_gating dbr:Fault_coverage dbr:Feedback-controlled_electromigration dbr:Hardware_obfuscation dbr:Hardware_watermarking dbr:Physical_design_(electronics) dbr:Programmable_logic_array dbr:Standard_cell dbr:Transaction-level_modeling dbr:Maze_runner dbr:Data_processing_unit dbr:Dolphin_Integration dbr:Gajski–Kuhn_chart dbr:Logic_simulation dbr:Logic_synthesis dbr:Power_optimization_(EDA) dbr:Cell_(EDA) dbr:Central_processing_unit dbr:Digital_electronics dbr:Floorplan_(microelectronics) dbr:Graphical_system_design dbr:Graphics_processing_unit dbr:Lee_algorithm dbr:Semiconductor_intellectual_property_core dbr:Power_gating dbr:Register-transfer_level dbr:High-level_synthesis dbr:Asynchronous_system dbr:Black's_equation dbr:High-level_verification dbr:Touchstone_file dbr:Boolean_satisfiability_problem dbr:Planar_SAT dbr:Circuit_extraction dbr:Fiduccia–Mattheyses_algorithm dbr:Semiconductor_process_simulation dbr:Schematic_capture dbr:Mask_data_preparation dbr:Multi-project_wafer_service dbr:Satisfiability_modulo_theories dbr:SCALD dbr:Signal_integrity dbr:Universal_Verification_Methodology dbr:VISC_architecture dbr:IC_layout_editor dbr:IEC_61131-3 dbr:Placement_(electronic_design_automation) dbr:Platform-based_design dbr:Rent's_rule dbr:Test_compression dbr:Simulation_software dbr:PBIST dbr:Place_and_route dbr:Multi-channel_length dbr:Stuck-at_fault dbr:Semiconductor_device_modeling dbr:Substrate_coupling dbr:Signoff_(electronic_design_automation) dbr:Resolution_enhancement_technologies dbr:Power_network_design_(IC) dbr:Schematic_editor dbr:Systems_design dbr:Technology_CAD
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