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- The EnCore microprocessor family is a configurable and extendable implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family:
* 5 stage pipeline
* highest operating frequency in its class
* lowest possible dynamic energy consumption - 99% of flip-flops automatically clock-gated using typical synthesis tools
* most non-memory operations achieving single-cycle latency, and no more than one load-delay slot
* easy configurability of cache architectures
* compact baseline instruction set architecture (ISA), including freely-mixed 16-bit and 32-bit encodings for maximum code density
* no overhead for switching between 16- and 32-bit instruction encodings All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these. The second, Castle, is named after the rock on which Edinburgh Castle is built. (en)
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- The EnCore microprocessor family is a configurable and extendable implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family: All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these. The second, Castle, is named after the rock on which Edinburgh Castle is built. (en)
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