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- High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is of less concern today. High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development 1.
* to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods 2.
* to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through logic simulation. (en)
- 高级验证（英語：High-level verification, HLV），或称系统级验证，是指在高抽象级别（层次）对所设计的电路系统进行验证的任务。高级验证主要是检验高抽象级别（通常在寄存器传输级之上）的模型设计是否代表了实际的硬件电路。高级验证与高级综合的关系，正类似功能验证和逻辑综合的关系。 数字电子系统设计已经从低抽象级别，即逻辑门级的设计，发展到寄存器传输级的设计。高于寄存器传输级的抽象层次，通常被称为“高级”，或“系统级”、“行为算法级”。 在高级综合里，系统的行为、算法设计通常以C语言、C++和SystemC代码等来书写，通过高级综合，这些代码被转换到寄存器传输级，然后再通过逻辑综合转换到逻辑门级的网表。功能验证被用来确保寄存器传输级或逻辑门级的硬件表示在功能上与设计目标一致。由于逻辑综合工具不断发展，大多数功能验证都在寄存器传输级完成，而非逻辑门级。现在，逻辑综合工具已经足够可靠，因此人们不像以前那样重点关注从寄存器传输级描述到逻辑门级的转换过程的功能验证。 时至今日，高级综合仍然是一种新兴技术。目前，高级验证有两个重要的研究领域： 1.
* 保证高级综合的翻译过程的正确性，通常通过形式验证的方式进行； 2.
* 保证用C语言、C++、SystemC代码书写的设计与预期目的符合，这一步通常用计算机仿真来完成。 (zh)
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- 高级验证（英語：High-level verification, HLV），或称系统级验证，是指在高抽象级别（层次）对所设计的电路系统进行验证的任务。高级验证主要是检验高抽象级别（通常在寄存器传输级之上）的模型设计是否代表了实际的硬件电路。高级验证与高级综合的关系，正类似功能验证和逻辑综合的关系。 数字电子系统设计已经从低抽象级别，即逻辑门级的设计，发展到寄存器传输级的设计。高于寄存器传输级的抽象层次，通常被称为“高级”，或“系统级”、“行为算法级”。 在高级综合里，系统的行为、算法设计通常以C语言、C++和SystemC代码等来书写，通过高级综合，这些代码被转换到寄存器传输级，然后再通过逻辑综合转换到逻辑门级的网表。功能验证被用来确保寄存器传输级或逻辑门级的硬件表示在功能上与设计目标一致。由于逻辑综合工具不断发展，大多数功能验证都在寄存器传输级完成，而非逻辑门级。现在，逻辑综合工具已经足够可靠，因此人们不像以前那样重点关注从寄存器传输级描述到逻辑门级的转换过程的功能验证。 时至今日，高级综合仍然是一种新兴技术。目前，高级验证有两个重要的研究领域： 1.
* 保证高级综合的翻译过程的正确性，通常通过形式验证的方式进行； 2.
* 保证用C语言、C++、SystemC代码书写的设计与预期目的符合，这一步通常用计算机仿真来完成。 (zh)
- High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. (en)
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- High-level verification (en)
- 高级验证 (zh)
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