About: Load–store architecture

Property	Value
dbo:description	Prozessorarchitektur (de) type of instruction set architecture (en) Arquitectura Load/store(processadors) (ca) instructiesetarchitectuur (nl)
dbo:wikiPageWikiLink	dbr:Instruction_set_architecture dbc:Computer_architecture dbr:Arithmetic_logic_unit dbr:PowerPC dbr:MIPS_architecture dbr:SPARC dbr:Computer_engineering dbr:Processor_register dbr:Load–store_unit dbr:X86 dbr:Vector_processor dbr:RISC-V dbr:CDC_6600 dbr:Register–memory_architecture dbr:GPUs dbr:Memory_(computing) dbr:ARM_architecture dbr:Complex_instruction_set_computing dbr:Reduced_instruction_set_computing dbr:Register-memory_architecture dbr:Load_and_store
dbp:date	June 2020 (en)
dbp:reason	In need of a better source to explain how 'many' GPUs use load–store than a datasheet on a particular architecture. (en)
dbp:wikiPageUsesTemplate	dbt:Comp-eng-stub dbt:Reflist dbt:Better_source dbt:Rp dbt:Short_description
dct:subject	dbc:Computer_architecture
rdfs:label	Load–store architecture (en) Load/store (processadors) (ca) Architektura load/store (cs) Load/Store-Architektur (de) Arquitectura de carga-almacenamiento (es) Arsitektur muat dan simpan (in) Архітектура load-store (uk) 載入-儲存架構 (zh)
owl:sameAs	wikidata:Load–store architecture dbpedia-de:Load–store architecture dbpedia-zh:Load–store architecture dbpedia-es:Load–store architecture dbpedia-id:Load–store architecture dbpedia-ca:Load–store architecture dbpedia-cs:Load–store architecture dbpedia-uk:Load–store architecture dbpedia-global:Load–store architecture
prov:wasDerivedFrom	wikipedia-en:Load–store_architecture?oldid=1255142302&ns=0
foaf:isPrimaryTopicOf	wikipedia-en:Load–store_architecture
is dbo:wikiPageRedirects of	dbr:Load–store dbr:Load/store_architecture dbr:Load-store_architecture
is dbo:wikiPageWikiLink of	dbr:HP_Saturn dbr:Instruction_set_architecture dbr:Comparison_of_instruction_set_architectures dbr:Asynchronous_circuit dbr:PowerPC dbr:Data_General_Nova dbr:Glossary_of_computer_hardware_terms dbr:Idempotence dbr:Load-link/store-conditional dbr:ARM_architecture_family dbr:Microarchitecture dbr:DLX dbr:Complex_instruction_set_computer dbr:Hardware_acceleration dbr:Infineon_TriCore dbr:Load–store_unit dbr:High-level_language_computer_architecture dbr:RISC-V dbr:CDC_6000_series dbr:Register–memory_architecture dbr:Power10 dbr:Load/store_architecture dbr:Load-store_architecture
is dbp:type of	dbr:Cell_(processor) dbr:ARC_(processor) dbr:PowerPC dbr:Motorola_88000 dbr:MIPS_architecture dbr:ARM_architecture_family dbr:SPARC dbr:DLX dbr:Blackfin dbr:Intel_i860 dbr:Infineon_TriCore dbr:IBM_ROMP dbr:Power_ISA dbr:IA-64 dbr:RISC-V dbr:DEC_Alpha dbr:LatticeMico32 dbr:ESi-RISC dbr:Qualcomm_Hexagon
is foaf:primaryTopic of	wikipedia-en:Load–store_architecture