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About:
Instruction processing
An Entity of Type:
Concept
,
from Named Graph:
http://dbpedia.org
,
within Data Space:
dbpedia.org
Property
Value
dbo:
wikiPageID
5991922
(xsd:integer)
dbo:
wikiPageRevisionID
934961838
(xsd:integer)
dbp:
wikiPageUsesTemplate
dbt
:Commonscat
rdf:
type
skos
:Concept
rdfs:
label
Instruction processing
(en)
skos:
broader
dbc
:Microprocessors
dbc
:Computer_architecture
skos:
prefLabel
Instruction processing
(en)
prov:
wasDerivedFrom
wikipedia-en
:Category:Instruction_processing?oldid=934961838&ns=14
is
dbo:
wikiPageWikiLink
of
dbr
:Predication_(computer_architecture)
dbr
:Minimal_instruction_set_computer
dbr
:Memory_barrier
dbr
:Anticiparallelism
dbr
:Application-specific_instruction_set_processor
dbr
:Register_window
dbr
:Reservation_station
dbr
:Cycle_time_(software)
dbr
:Cycles_per_instruction
dbr
:Decoupled_architecture
dbr
:Degree_of_parallelism
dbr
:Delay_slot
dbr
:Instruction_cycle
dbr
:Instruction_pipelining
dbr
:Instruction_prefetch
dbr
:Instruction_window
dbr
:Instructions_per_cycle
dbr
:Interlock_(engineering)
dbr
:Wide-issue
dbr
:General-purpose_computing_on_graphics_processing_units
dbr
:Out-of-order_execution
dbr
:Runahead
dbr
:Branch_(computer_science)
dbr
:Branch_misprediction
dbr
:Branch_predictor
dbr
:Branch_target_predictor
dbr
:Multithreading_(computer_architecture)
dbr
:Control_store
dbr
:Millicode
dbr
:Orthogonal_instruction_set
dbr
:Berkeley_RISC
dbr
:MIL-STD-1750A
dbr
:Hardware_reset
dbr
:Microarchitecture
dbr
:Pipeline_(computing)
dbr
:Prefetch_input_queue
dbr
:VIA_PadLock
dbr
:Pipeline_stall
dbr
:Speculative_execution
dbr
:Transport_triggered_architecture
dbr
:Micro-operation
dbr
:Microcode
dbr
:Address_generation_unit
dbr
:Hazard_(computer_architecture)
dbr
:Barrel_processor
dbr
:No_instruction_set_computing
dbr
:Operand_forwarding
dbr
:Hardware_scout
dbr
:Random_logic
dbr
:TRIPS_architecture
dbr
:Burroughs_B6x00-7x00_instruction_set
dbr
:Speculative_multithreading
dbr
:Classic_RISC_pipeline
dbr
:Instruction-level_parallelism
dbr
:Instruction_set_architecture
dbr
:Re-order_buffer
dbr
:Memory-level_parallelism
dbr
:Model-specific_register
dbr
:Slipstream_(computer_science)
dbr
:Tomasulo's_algorithm
dbr
:Explicitly_parallel_instruction_computing
dbr
:Very_long_instruction_word
dbr
:Zero_instruction_set_computer
dbr
:Execute_instruction
dbr
:Scoreboarding
dbr
:Reset_vector
dbr
:Repeat_instruction
dbr
:Unicore
is
dcterms:
subject
of
dbr
:Predication_(computer_architecture)
dbr
:Minimal_instruction_set_computer
dbr
:Memory_barrier
dbr
:Anticiparallelism
dbr
:Application-specific_instruction_set_processor
dbr
:Register_window
dbr
:Reservation_station
dbr
:Cycle_time_(software)
dbr
:Cycles_per_instruction
dbr
:Decoupled_architecture
dbr
:Degree_of_parallelism
dbr
:Delay_slot
dbr
:Instruction_cycle
dbr
:Instruction_pipelining
dbr
:Instruction_prefetch
dbr
:Instruction_window
dbr
:Instructions_per_cycle
dbr
:Interlock_(engineering)
dbr
:Wide-issue
dbr
:General-purpose_computing_on_graphics_processing_units
dbr
:Out-of-order_execution
dbr
:Runahead
dbr
:Branch_(computer_science)
dbr
:Branch_misprediction
dbr
:Branch_predictor
dbr
:Branch_target_predictor
dbr
:Multithreading_(computer_architecture)
dbr
:Control_store
dbr
:Millicode
dbr
:Orthogonal_instruction_set
dbr
:Berkeley_RISC
dbr
:MIL-STD-1750A
dbr
:Hardware_reset
dbr
:Microarchitecture
dbr
:Pipeline_(computing)
dbr
:Prefetch_input_queue
dbr
:VIA_PadLock
dbr
:Pipeline_stall
dbr
:Speculative_execution
dbr
:Transport_triggered_architecture
dbr
:Micro-operation
dbr
:Microcode
dbr
:Address_generation_unit
dbr
:Hazard_(computer_architecture)
dbr
:Barrel_processor
dbr
:No_instruction_set_computing
dbr
:Operand_forwarding
dbr
:Hardware_scout
dbr
:Random_logic
dbr
:TRIPS_architecture
dbr
:Burroughs_B6x00-7x00_instruction_set
dbr
:Speculative_multithreading
dbr
:Classic_RISC_pipeline
dbr
:Instruction-level_parallelism
dbr
:Instruction_set_architecture
dbr
:Re-order_buffer
dbr
:Memory-level_parallelism
dbr
:Model-specific_register
dbr
:Slipstream_(computer_science)
dbr
:Tomasulo's_algorithm
dbr
:Explicitly_parallel_instruction_computing
dbr
:Very_long_instruction_word
dbr
:Zero_instruction_set_computer
dbr
:Execute_instruction
dbr
:Scoreboarding
dbr
:Reset_vector
dbr
:Repeat_instruction
dbr
:Unicore
is
skos:
broader
of
dbc
:Very_long_instruction_word_computing
dbc
:Speculative_execution
dbc
:Machine_code
dbc
:SIMD_computing
dbc
:GPGPU
dbc
:Superscalar_microprocessors
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