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- On VIA Nehemiah and Antaur CPUs , bits 0,1,4,5 are used differently:
* Bit 0: Alternate Instruction Set present
* Bit 1: AIS enabled
* Bit 4: LongHaul MSR present
* Bit 5: instruction present (en)
- On some processors - Cyrix MediaGXm, several Geodes and Transmeta Crusoe - EDX bits 16 and 24 have a different meaning:
* Bit 16: Floating-point Conditional Move supported
* Bit 24: 6x86MX Extended MMX instructions supported (en)
- For the associativity fields of leaf , the following values are used:
class="wikitable sortable"
! Value !! Meaning
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0
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1 Direct-mapped
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2 to N-way set-associative
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Fully-associative (en)
- As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel TDX documentation and are not set in any known processor. (en)
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