About: Verilog-AMS

Facets (new session)
Description
Metadata
Settings
- Rule:
- Inverse Functional Properties:
- "Same As":

About: Verilog-AMS Goto Sponge NotDistinct Permalink

An Entity of Type : yago:WikicatHardwareDescriptionLanguages, within Data Space : dbpedia.org associated with source document(s)
QRcode icon

http://dbpedia.org/describe/?url=http%3A%2F%2Fdbpedia.org%2Fresource%2FVerilog-AMS

Verilog-AMS is a derivative of the Verilog hardware description language that includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.

Attributes	Values
rdf:type	chemical substance yago:WikicatComputerLanguages yago:Abstraction100002137 yago:ArtificialLanguage106894544 yago:Communication100033020 yago:ComputerLanguage106899633 yago:Language106282651 yago:ProgrammingLanguage106898352 yago:WikicatHardwareDescriptionLanguages
rdfs:label	Verilog-AMS (fr) Verilog-AMS (ja) Verilog-AMS (ru) Verilog-AMS (en) Verilog-AMS (zh)
rdfs:comment	Verilog-AMS is a derivative of the Verilog hardware description language that includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa. (en) Verilog-AMSは、アナログ回路とディジタル回路の混在した回路(いわゆるミックスドシグナル)の動作を定義するためのアナログおよびミックスドシグナル拡張（AMS）を含むVerilogハードウェア記述言語の派生語である。 (ja) Verilog-AMS (от Verilog Analog Mixed-Signal Simulation) — язык описания и моделирования аппаратуры, был создан компанией Accellera на основе и Verilog-D с дополнительными возможностями, целью которого является работа с , аналогово- системами и интегральными микросхемами, использование модулей, на высоких уровнях и систем и её компонент. (ru) Verilog-AMS是Verilog硬件描述语言的一个衍生。它包含了模拟和混合信号扩展模块，以实现对于模拟电路和混合信号系统行为的描述。它扩展了Verilog、SystemVerilog等的事件驱动仿真器的回路，通过使用一个连续时间仿真器，可以在模拟域（analog-domain）上求解微分方程。模拟事件可以触发数字行为，反之亦可。 (zh) Verilog-AMS est un dérivé du langage de description matériel Verilog. Il comprend des extensions analogiques et des signaux mixtes (en anglais analog and mixed-signal, AMS) afin de définir le comportement des systèmes à signaux analogiques et mixtes. La norme Verilog-AMS a été instaurée dans l'intention de permettre aux concepteurs de systèmes à signaux analogiques et mixtes et de circuits intégrés de pouvoir créer et d'utiliser des modules qui encapsulent les descriptions de comportement de haut niveau, aussi bien que des descriptions structurelles de systèmes et de composants (fr)
dcterms:subject	Hardware description languages
Wikipage page ID	5588193 (xsd:integer)
Wikipage revision ID	1112992116 (xsd:integer)
Link from a Wikipage to another Wikipage	Verilog Verilog-A VHDL-AMS Analog-to-digital converter Accellera Hardware description language Hardware description languages Digital-to-analog converter Verilog Procedural Interface
Link from a Wikipage to an external page	http://ovams.sourceforge.net/ http://www.v-ms.com/ http://www.verilogams.com http://www.designers-guide.org/VerilogAMS/ https://web.archive.org/web/20070927051749/http:/www.nsti.org/publ/MSM2000/T31.01.pdf http://www.accellera.org/activities/committees/verilog-ams/ http://www.eda.org/twiki/bin/view.cgi/VerilogAMS
sameAs	Verilog-AMS Verilog-AMS Verilog-AMS Verilog-AMS Verilog-AMS Verilog-AMS Verilog-AMS Verilog-AMS
dbp:wikiPageUsesTemplate	dbt:Short_description dbt:Use_American_English dbt:Programmable_Logic
has abstract	Verilog-AMS est un dérivé du langage de description matériel Verilog. Il comprend des extensions analogiques et des signaux mixtes (en anglais analog and mixed-signal, AMS) afin de définir le comportement des systèmes à signaux analogiques et mixtes. La norme Verilog-AMS a été instaurée dans l'intention de permettre aux concepteurs de systèmes à signaux analogiques et mixtes et de circuits intégrés de pouvoir créer et d'utiliser des modules qui encapsulent les descriptions de comportement de haut niveau, aussi bien que des descriptions structurelles de systèmes et de composants Verilog-AMS définit un langage de modélisation standardisé par l'industrie pour les circuits à signaux mixtes. Il fournit à la fois le temps-continu et les sémantiques de modélisation d'événements. Il est donc approprié pour les circuits analogiques, numériques et mixtes. Il important de noter que le Verilog ne constitue pas un langage de programmation. Il s'agit d'un langage de description du matériel. (fr) Verilog-AMS is a derivative of the Verilog hardware description language that includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa. (en) Verilog-AMSは、アナログ回路とディジタル回路の混在した回路(いわゆるミックスドシグナル)の動作を定義するためのアナログおよびミックスドシグナル拡張（AMS）を含むVerilogハードウェア記述言語の派生語である。 (ja) Verilog-AMS (от Verilog Analog Mixed-Signal Simulation) — язык описания и моделирования аппаратуры, был создан компанией Accellera на основе и Verilog-D с дополнительными возможностями, целью которого является работа с , аналогово- системами и интегральными микросхемами, использование модулей, на высоких уровнях и систем и её компонент. (ru) Verilog-AMS是Verilog硬件描述语言的一个衍生。它包含了模拟和混合信号扩展模块，以实现对于模拟电路和混合信号系统行为的描述。它扩展了Verilog、SystemVerilog等的事件驱动仿真器的回路，通过使用一个连续时间仿真器，可以在模拟域（analog-domain）上求解微分方程。模拟事件可以触发数字行为，反之亦可。 (zh)
gold:hypernym	Derivative
prov:wasDerivedFrom	wikipedia-en:Verilog-AMS?oldid=1112992116&ns=0
page length (characters) of wiki page	6303 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Verilog-AMS
is Link from a Wikipage to another Wikipage of	Cadence Design Systems Behavioral modeling in computer-aided design Electrical network List of concurrent and parallel programming languages Verilog Verilog-A VHDL-AMS List of programming languages by type Analog verification Comparison of EDA software Accellera Flow to HDL Ken Kundert AMS Hardware description language ADMS Bluespec SystemVerilog TINA (program) Saber (software) NCSim
is Wikipage disambiguates of	AMS
is dialects of	Verilog
is foaf:primaryTopic of	wikipedia-en:Verilog-AMS

Faceted Search & Find service v1.17_git139 as of Feb 29 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 08.03.3330 as of Mar 19 2024, on Linux (x86_64-generic-linux-glibc212), Single-Server Edition (62 GB total memory, 54 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software