About: Verilog-A

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Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format.

Attributes	Values
rdf:type	language yago:Abstraction100002137 yago:Communication100033020 yago:Language106282651 yago:WikicatHardwareDescriptionLanguages
rdfs:label	Verilog-A (es) Verilog-A (en) Verilog-A (zh)
rdfs:comment	Verilog-A es un lenguaje de modelamiento estándar en la industria para circuitos analógicos. Es un 'subset' de Verilog-AMS con la característica de ser continuo a través del tiempo. (es) Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format. (en) Verilog-A是一种针对模拟电路的工业标准模型语言，它是 Verilog-AMS的连续时间子集。 Verilog-A被设计用来对Spectre电路仿真器（Spectre Circuit Simulator）的行为级描述进行标准化，以实现与VHDL（另一个IEEE标准支持的硬件描述语言）。它从其他语言（例如MAST）吸收了对模拟电路的支持。国际Verilog开放组织（Open Verilog International, OVI）支持 Verilog的标准化，使得Verilog-A作为整个Verilog-AMS计划的一部分，从而实现对模拟电路和数字电路设计的处理能力。Verilog-A是Verilog-AMS项目的最初阶段发展起来的。不过，Verilog的开发进展与Verilog-AMS延迟不同，而当时Verilog被纳入了IEEE 1364标准，这就使得Verilog-AMS被遗留给了Accellera公司。因此最初的单一语言标准的目标并没有实现。 (zh)
dcterms:subject	Hardware description languages
Wikipage page ID	7649454 (xsd:integer)
Wikipage revision ID	1062479451 (xsd:integer)
Link from a Wikipage to another Wikipage	Programming language reference VHDL Verilog Verilog-AMS Spectre Circuit Simulator Accellera BSIM ADMS Hardware description languages SystemVerilog Ngspice C programming language MEMS
Link from a Wikipage to an external page	http://www.eda.org/verilog-ams/ http://designers-guide.org/Books/dg-vams/index.html http://www.verilogams.com http://www.designers-guide.org/VerilogAMS http://www.accellera.org/downloads/standards/v-ams http://www.eda.org/verilog-ams/hm/ http://www.eda.org/verilog-ams/htmlpages/dod.html http://www.eda.org/verilog-ams/htmlpages/lit.html
sameAs	Verilog-A Verilog-A Verilog-A Verilog-A Verilog-A Verilog-A
dbp:wikiPageUsesTemplate	dbt:Cleanup dbt:Multiple_issues dbt:Refimprove dbt:Reflist dbt:Programmable_Logic
has abstract	Verilog-A es un lenguaje de modelamiento estándar en la industria para circuitos analógicos. Es un 'subset' de Verilog-AMS con la característica de ser continuo a través del tiempo. (es) Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format. (en) Verilog-A是一种针对模拟电路的工业标准模型语言，它是 Verilog-AMS的连续时间子集。 Verilog-A被设计用来对Spectre电路仿真器（Spectre Circuit Simulator）的行为级描述进行标准化，以实现与VHDL（另一个IEEE标准支持的硬件描述语言）。它从其他语言（例如MAST）吸收了对模拟电路的支持。国际Verilog开放组织（Open Verilog International, OVI）支持 Verilog的标准化，使得Verilog-A作为整个Verilog-AMS计划的一部分，从而实现对模拟电路和数字电路设计的处理能力。Verilog-A是Verilog-AMS项目的最初阶段发展起来的。不过，Verilog的开发进展与Verilog-AMS延迟不同，而当时Verilog被纳入了IEEE 1364标准，这就使得Verilog-AMS被遗留给了Accellera公司。因此最初的单一语言标准的目标并没有实现。 (zh)
gold:hypernym	Language
prov:wasDerivedFrom	wikipedia-en:Verilog-A?oldid=1062479451&ns=0
page length (characters) of wiki page	5555 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Verilog-A
is Link from a Wikipage to another Wikipage of	Cadence Design Systems Electronic circuit simulation SmartSpice Verilog Verilog-AMS Comparison of EDA software Spectre Circuit Simulator Flow to HDL Ken Kundert BSIM ADMS TINA (program) Quite Universal Circuit Simulator Multigate device VerilogA
is Wikipage redirect of	VerilogA
is foaf:primaryTopic of	wikipedia-en:Verilog-A

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