About: VerilogCSP

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In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

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  • In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack. (en)
  • 在集成电路设计中，VerilogCSP是Verilog硬件描述语言的一个宏，目的是为了支持通信顺序进程（CSP）。这个宏可以用来进行同步数字电路的设计。 VerilogCSP还可以描述非线性流水线结构高级别通道的时间属性，正向或负向的时间延迟，最小循环时间等。 (zh)
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  • In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack. (en)
  • 在集成电路设计中，VerilogCSP是Verilog硬件描述语言的一个宏，目的是为了支持通信顺序进程（CSP）。这个宏可以用来进行同步数字电路的设计。 VerilogCSP还可以描述非线性流水线结构高级别通道的时间属性，正向或负向的时间延迟，最小循环时间等。 (zh)
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  • VerilogCSP (en)
  • VerilogCSP (zh)
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