An Entity of Type: person, from Named Graph: http://dbpedia.org, within Data Space: dbpedia.org

Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with multithreading. It is different from SPMD in that all instructions in all "threads" are executed in lock-step. The SIMT execution model has been implemented on several GPUs and is relevant for general-purpose computing on graphics processing units (GPGPU), e.g. some supercomputers combine CPUs with GPUs.

Property Value
dbo:abstract
  • SIMT (de l'anglais : Single Instruction, Multiple Threads, selon la taxonomie de Flynn) est une amélioration de SIMD (de l'anglais : Single Instruction, Multiple Data) qui permettait sur des processeur arithmétique spécialisés de faire des calculs sur plusieurs données en une seule instruction, en l'adaptant au calcul multithread (c'est-à-dire, comportant plusieurs files d'exécution). (fr)
  • Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with multithreading. It is different from SPMD in that all instructions in all "threads" are executed in lock-step. The SIMT execution model has been implemented on several GPUs and is relevant for general-purpose computing on graphics processing units (GPGPU), e.g. some supercomputers combine CPUs with GPUs. The processors, say a number p of them, seem to execute many more than p tasks. This is achieved by each processor having multiple "threads" (or "work-items" or "Sequence of SIMD Lane operations"), which execute in lock-step, and are analogous to SIMD lanes. The simplest way to understand SIMT is to imagine a multi-core system, where each core has its own register file, its own ALUs (both SIMD and Scalar) and its own data cache, but that unlike a standard multi-core system which has multiple independent instruction caches and decoders, as well as multiple independent Program Counter registers, the instructions are synchronously broadcast to all SIMT cores from a single unit with a single instruction cache and a single instruction decoder which reads instructions using a single Program Counter. The key difference between SIMT and SIMD lanes is that each of the SIMT cores may have a completely different Stack Pointer (and thus perform computations on completely different data sets), whereas SIMD lanes are simply part of an ALU that know nothing about memory per se. (en)
dbo:wikiPageID
  • 43320329 (xsd:integer)
dbo:wikiPageLength
  • 6957 (xsd:nonNegativeInteger)
dbo:wikiPageRevisionID
  • 1123650169 (xsd:integer)
dbo:wikiPageWikiLink
dbp:wikiPageUsesTemplate
dcterms:subject
gold:hypernym
rdf:type
rdfs:comment
  • SIMT (de l'anglais : Single Instruction, Multiple Threads, selon la taxonomie de Flynn) est une amélioration de SIMD (de l'anglais : Single Instruction, Multiple Data) qui permettait sur des processeur arithmétique spécialisés de faire des calculs sur plusieurs données en une seule instruction, en l'adaptant au calcul multithread (c'est-à-dire, comportant plusieurs files d'exécution). (fr)
  • Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with multithreading. It is different from SPMD in that all instructions in all "threads" are executed in lock-step. The SIMT execution model has been implemented on several GPUs and is relevant for general-purpose computing on graphics processing units (GPGPU), e.g. some supercomputers combine CPUs with GPUs. (en)
rdfs:label
  • SIMT (fr)
  • Single instruction, multiple threads (en)
owl:sameAs
prov:wasDerivedFrom
foaf:isPrimaryTopicOf
is dbo:wikiPageDisambiguates of
is dbo:wikiPageRedirects of
is dbo:wikiPageWikiLink of
is foaf:primaryTopic of
Powered by OpenLink Virtuoso    This material is Open Knowledge     W3C Semantic Web Technology     This material is Open Knowledge    Valid XHTML + RDFa
This content was extracted from Wikipedia and is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License