About: Dynamic timing verification

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Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is accomplished by simulating the design files used to synthesize the integrated circuit (IC) design. This is in contrast to static timing analysis, which has a similar goal as dynamic timing verification except it does not require simulating the real functionality of the IC.

Attributes	Values
rdf:type	yago:Ability105616246 yago:Abstraction100002137 yago:Cognition100023271 yago:Know-how105616786 yago:Method105660268 yago:PsychologicalFeature100023100 yago:WikicatFormalMethods
rdfs:label	Dynamic timing verification (en) 动态时序验证 (zh)
rdfs:comment	动态时序验证（英語：Dynamic timing verification）是指对专用集成电路的一种验证过程，它被用来检查电路是否能够以足够快的速率在指定的时钟频率下正常。将用于集成电路综合过程的设计文件进行仿真，动态时序验证得以进行。该过程与静态时序分析相对应，后者与动态时序验证有着相似的目标，但是它并不需要对集成电路的实际功能进行仿真。 (zh) Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is accomplished by simulating the design files used to synthesize the integrated circuit (IC) design. This is in contrast to static timing analysis, which has a similar goal as dynamic timing verification except it does not require simulating the real functionality of the IC. (en)
dcterms:subject	Timing in electronic circuits Formal methods
Wikipage page ID	31479005 (xsd:integer)
Wikipage revision ID	620755679 (xsd:integer)
Link from a Wikipage to another Wikipage	Application-specific integrated circuit Integrated circuit Timing in electronic circuits Formal methods Static timing analysis
sameAs	Dynamic timing verification Dynamic timing verification Dynamic timing verification Dynamic timing verification Dynamic timing verification
dbp:wikiPageUsesTemplate	dbt:Reflist
has abstract	Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is accomplished by simulating the design files used to synthesize the integrated circuit (IC) design. This is in contrast to static timing analysis, which has a similar goal as dynamic timing verification except it does not require simulating the real functionality of the IC. Hobbyists often perform a type of dynamic timing verification when they over-clock the CPUs in their computers in order to find the fastest clock rate at which they can run the CPU without errors. This is a type of dynamic timing verification that is performed after the silicon is manufactured. In the field of ASIC design, this timing verification is preferably performed before manufacturing the IC in order to make sure that IC works under the required conditions before mass production of the IC. (en) 动态时序验证（英語：Dynamic timing verification）是指对专用集成电路的一种验证过程，它被用来检查电路是否能够以足够快的速率在指定的时钟频率下正常。将用于集成电路综合过程的设计文件进行仿真，动态时序验证得以进行。该过程与静态时序分析相对应，后者与动态时序验证有着相似的目标，但是它并不需要对集成电路的实际功能进行仿真。 (zh)
prov:wasDerivedFrom	wikipedia-en:Dynamic_timing_verification?oldid=620755679&ns=0
page length (characters) of wiki page	1175 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Dynamic_timing_verification
is Link from a Wikipage to another Wikipage of	Standard Delay Format Static timing analysis
is foaf:primaryTopic of	wikipedia-en:Dynamic_timing_verification

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