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Static timing analysis (STA) is a simulation method of computing the expected timing of a synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Measuring the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an app

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rdf:type	software yago:Ability105616246 yago:Abstraction100002137 yago:Cognition100023271 yago:Know-how105616786 yago:Method105660268 yago:PsychologicalFeature100023100 yago:WikicatFormalMethods
rdfs:label	Analyse temporelle statique (fr) Static timing analysis (en) Статический временной анализ (ru) 静态时序分析 (zh)
rdfs:comment	Статический временной анализ (СВА, англ. Static timing analysis) — это метод расчёта временных параметров СБИС, не требующий полноценного электрического моделирования работы схемы. (ru) 静态时序分析（英語：Static Timing Analysis, STA），或称静态时序验证，是电子工程中，对数字电路的时序进行计算、预计的工作流程，该流程不需要通过输入激励的方式进行仿真。传统上，人们常常将工作时钟频率作为高性能的集成电路的特性之一。为了测试电路在指定速率下运行的能力，人们需要在设计过程中测量电路在不同工作阶段的延迟。此外，在不同的设计阶段（例如逻辑综合、布局、布线以及一些后续阶段）需要对时间优化程序内部进行（Delay calculation）。尽管可以通过严格的SPICE电路仿真来进行此类时间测量，但是这种方法在实用中耗费大量时间。静态时序分析在电路时序快速、准确的测量中扮演了重要角色。静态时序分析能够更快速地完成任务，是因为它使用了简化的模型，而且它有限地考虑了信号之间的逻辑互动。静态时序分析在最近几十年中，成为了相关设计领域中的主要技术方法。静态时序分析的最早描述之一是基于1966年的計畫評核術。它的一些更现代的版本和算法则出现于1980年代前期。 (zh) L’analyse temporelle statique (en anglais : static timing analysis, TSA) est une méthode d'évaluation de la fréquence de fonctionnement d'un circuit intégré. Contrairement à l'analyse dynamique, elle ne nécessite pas l'usage de vecteur de test ni de simulation.Elle repose sur le calcul et l'addition des délais de chaque porte logique élémentaire d'un circuit. (fr) Static timing analysis (STA) is a simulation method of computing the expected timing of a synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Measuring the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an app (en)
dcterms:subject	Timing in electronic circuits Formal methods
Wikipage page ID	2546747 (xsd:integer)
Wikipage revision ID	1060948585 (xsd:integer)
Link from a Wikipage to another Wikipage	Electronic design automation Delay calculation Depth-first search Dynamic timing verification Integrated circuit Integrated circuit design SPICE Clock skew Model checking Monotonic Timing in electronic circuits Critical path method Clock signal Placement (EDA) Lockstep (computing) Logic analyzer Logic simulation Logic synthesis Flip-flop (electronics) Synchronous circuit Program Evaluation and Review Technique Formal methods Statistical static timing analysis Simulation Worst-case execution time Timing margin Process corners Signoff (electronic design automation) Routing (EDA) Arrival time Glitches Latch (electronic) Clock frequency
sameAs	Static timing analysis Static timing analysis Static timing analysis Static timing analysis Static timing analysis Static timing analysis Static timing analysis
dbp:wikiPageUsesTemplate	dbt:ISBN dbt:More_citations_needed dbt:Reflist dbt:Short_description dbt:Use_American_English dbt:Use_mdy_dates
has abstract	L’analyse temporelle statique (en anglais : static timing analysis, TSA) est une méthode d'évaluation de la fréquence de fonctionnement d'un circuit intégré. Contrairement à l'analyse dynamique, elle ne nécessite pas l'usage de vecteur de test ni de simulation.Elle repose sur le calcul et l'addition des délais de chaque porte logique élémentaire d'un circuit. L'analyse temporelle statique permet de calculer le plus long chemin logique d'un circuit, le chemin critique.En outre, elle permet de vérifier que les données reçues par un élément synchrone sont stables au moment où celui-ci reçoit un coup d'horloge. Ceci permet d'éviter des erreurs de hold ou de setup. (fr) Static timing analysis (STA) is a simulation method of computing the expected timing of a synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Measuring the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup comes from the use of simplified timing models and by mostly ignoring logical interactions in circuits. This has become a mainstay of design over the last few decades. One of the earliest descriptions of a static timing approach was based on the Program Evaluation and Review Technique (PERT), in 1966. More modern versions and algorithms appeared in the early 1980s. (en) Статический временной анализ (СВА, англ. Static timing analysis) — это метод расчёта временных параметров СБИС, не требующий полноценного электрического моделирования работы схемы. (ru) 静态时序分析（英語：Static Timing Analysis, STA），或称静态时序验证，是电子工程中，对数字电路的时序进行计算、预计的工作流程，该流程不需要通过输入激励的方式进行仿真。传统上，人们常常将工作时钟频率作为高性能的集成电路的特性之一。为了测试电路在指定速率下运行的能力，人们需要在设计过程中测量电路在不同工作阶段的延迟。此外，在不同的设计阶段（例如逻辑综合、布局、布线以及一些后续阶段）需要对时间优化程序内部进行（Delay calculation）。尽管可以通过严格的SPICE电路仿真来进行此类时间测量，但是这种方法在实用中耗费大量时间。静态时序分析在电路时序快速、准确的测量中扮演了重要角色。静态时序分析能够更快速地完成任务，是因为它使用了简化的模型，而且它有限地考虑了信号之间的逻辑互动。静态时序分析在最近几十年中，成为了相关设计领域中的主要技术方法。静态时序分析的最早描述之一是基于1966年的計畫評核術。它的一些更现代的版本和算法则出现于1980年代前期。 (zh)
gold:hypernym	Method
prov:wasDerivedFrom	wikipedia-en:Static_timing_analysis?oldid=1060948585&ns=0
page length (characters) of wiki page	10597 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Static_timing_analysis
is Link from a Wikipage to another Wikipage of	Electromagnetic field solver Electronic design automation Engineering change order Design closure Design flow (EDA) Application-specific integrated circuit Delay calculation Dynamic timing verification EDA database Reconvergent fan-out Timing closure Elmore delay Magma Design Automation Common Power Format Computer engineering compendium Hardware emulation Logic simulation Power optimization (EDA) Altos Design Automation Synchronous circuit List of EDA companies Processor design Circuit extraction Xilinx ISE STA Standard Delay Format

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