This HTML5 document contains 91 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
dbpedia-dehttp://de.dbpedia.org/resource/
dctermshttp://purl.org/dc/terms/
yago-reshttp://yago-knowledge.org/resource/
dbohttp://dbpedia.org/ontology/
foafhttp://xmlns.com/foaf/0.1/
n15https://global.dbpedia.org/id/
yagohttp://dbpedia.org/class/yago/
dbthttp://dbpedia.org/resource/Template:
rdfshttp://www.w3.org/2000/01/rdf-schema#
freebasehttp://rdf.freebase.com/ns/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
owlhttp://www.w3.org/2002/07/owl#
wikipedia-enhttp://en.wikipedia.org/wiki/
dbchttp://dbpedia.org/resource/Category:
dbphttp://dbpedia.org/property/
provhttp://www.w3.org/ns/prov#
xsdhhttp://www.w3.org/2001/XMLSchema#
n19http://www.analog.com/en/processors-dsp/sharc/products/
wikidatahttp://www.wikidata.org/entity/
goldhttp://purl.org/linguistics/gold/
dbrhttp://dbpedia.org/resource/
dbpedia-jahttp://ja.dbpedia.org/resource/

Statements

Subject Item
dbr:Blackfin
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:List_of_common_microcontrollers
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Delay_slot
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Intel_i860
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:SHARC_(chip)
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
dbo:wikiPageRedirects
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Analog_Devices_SHARC
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
dbo:wikiPageRedirects
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:ThreadX
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:GTI_Club
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Analog_Devices
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Fat_tree
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Digital_signal_processor
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Qualcomm_Hexagon
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:SHARC
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Very_long_instruction_word
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:TigerSHARC
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Super_Harvard_Architecture_Single-Chip_Computer
rdf:type
yago:Processor108065937 owl:Thing yago:WikicatDigitalSignalProcessors yago:Enterprise108056231 yago:SocialGroup107950920 yago:Organization108008335 yago:Business108061042 yago:YagoPermanentlyLocatedEntity yago:Group100031264 yago:YagoLegalActor yago:YagoLegalActorGeo yago:Abstraction100002137
rdfs:label
Super-Harvard-Architektur Super Harvard Architecture Single-Chip Computer Super Harvard Architecture Single-Chip Computer
rdfs:comment
The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994. SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP. Super Harvard Architecture Single-Chip Computer (SHARC)は、アナログ・デバイセズのDSPで、高性能な浮動小数点と固定小数点演算を特徴とする。SHARCは、幅広い信号処理用途に利用されており、CPU 1個による砲弾の制御から、CPU 1000個によりOTHレーダーの信号処理用コンピューターまで用途が存在する。SHARCは1994年1月ごろに設計された。 SHARCプロセッサーは、単位消費電力当たりの浮動小数点演算性能が良好であるため利用されている。 SHARCプロセッサーは、典型的には近隣のSHARCプロセッサーとシリアル接続されることで、低コストでSMPの代替として利用できるようになっている。 Super-Harvard-Architektur ist der von Analog Devices geprägte Begriff für eine Modifikation der Harvard-Architektur in digitalen Signalprozessoren.Die Erweiterung besteht darin, dass Befehle in einem Cache zwischengespeichert werden und der Befehlsbus für den Transfer von Operanden verwendet wird.Zudem wird durch direkten Datentransfer zwischen dem Befehls- und Datenspeicher der Prozessor von dieser Aufgabe entlastet.
owl:differentFrom
dbr:SuperH
dcterms:subject
dbc:VLIW_microprocessors dbc:Digital_signal_processors dbc:Very_long_instruction_word_computing
dbo:wikiPageID
1082845
dbo:wikiPageRevisionID
1110801526
dbo:wikiPageWikiLink
dbr:Fixed-point_arithmetic dbr:Operating_system dbr:VLIW dbc:VLIW_microprocessors dbc:Digital_signal_processors dbr:Delay_slot dbr:Octet_(computing) dbr:32-bit dbr:Audio_signal_processing dbc:Very_long_instruction_word_computing dbr:Texas_Instruments_TMS320 dbr:Direct_memory_access dbr:Symmetric_multiprocessing dbr:Qualcomm_Hexagon dbr:48-bit dbr:Blackfin dbr:Floating-point dbr:Analog_Devices dbr:Harvard_architecture dbr:CEVA,_Inc. dbr:Memory_management_unit dbr:Digital_signal_processor dbr:X86 dbr:Word_addressing dbr:TigerSHARC dbr:Assembly_language dbr:Overlay_(programming)
dbo:wikiPageExternalLink
n19:index.html
owl:sameAs
wikidata:Q2366992 yago-res:Super_Harvard_Architecture_Single-Chip_Computer n15:2Egqu dbpedia-ja:Super_Harvard_Architecture_Single-Chip_Computer freebase:m.044hlp dbpedia-de:Super-Harvard-Architektur
dbp:wikiPageUsesTemplate
dbt:Primary_sources dbt:Distinguish
dbo:abstract
The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994. SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP. Super-Harvard-Architektur ist der von Analog Devices geprägte Begriff für eine Modifikation der Harvard-Architektur in digitalen Signalprozessoren.Die Erweiterung besteht darin, dass Befehle in einem Cache zwischengespeichert werden und der Befehlsbus für den Transfer von Operanden verwendet wird.Zudem wird durch direkten Datentransfer zwischen dem Befehls- und Datenspeicher der Prozessor von dieser Aufgabe entlastet. Super Harvard Architecture Single-Chip Computer (SHARC)は、アナログ・デバイセズのDSPで、高性能な浮動小数点と固定小数点演算を特徴とする。SHARCは、幅広い信号処理用途に利用されており、CPU 1個による砲弾の制御から、CPU 1000個によりOTHレーダーの信号処理用コンピューターまで用途が存在する。SHARCは1994年1月ごろに設計された。 SHARCプロセッサーは、単位消費電力当たりの浮動小数点演算性能が良好であるため利用されている。 SHARCプロセッサーは、典型的には近隣のSHARCプロセッサーとシリアル接続されることで、低コストでSMPの代替として利用できるようになっている。
gold:hypernym
dbr:DSP
prov:wasDerivedFrom
wikipedia-en:Super_Harvard_Architecture_Single-Chip_Computer?oldid=1110801526&ns=0
dbo:wikiPageLength
4019
foaf:isPrimaryTopicOf
wikipedia-en:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Super_harvard_architecture
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
dbo:wikiPageRedirects
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Super_Harvard_architecture
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
dbo:wikiPageRedirects
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
dbr:Super_harvard
dbo:wikiPageWikiLink
dbr:Super_Harvard_Architecture_Single-Chip_Computer
dbo:wikiPageRedirects
dbr:Super_Harvard_Architecture_Single-Chip_Computer
Subject Item
wikipedia-en:Super_Harvard_Architecture_Single-Chip_Computer
foaf:primaryTopic
dbr:Super_Harvard_Architecture_Single-Chip_Computer