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- Das Standard Parasitic Exchange Format (SPEF) ist ein Dateiformat für den rechnergestützten Entwurf elektronischer Schaltungen. Mit diesem wird der elektrische Widerstand und die Kapazität sowie die Verzögerungszeit von Verdrahtungselementen beschrieben. Die Daten sind im SPICE-Format abgelegt. Das SPEF ist Teil des Standards IEEE 1481-1999. (de)
- Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Non-ideal wires have parasitic resistance and capacitance that are captured by SPEF. These wires also have inductance that is not included in SPEF. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation. SPEF is the most popular specification for parasitic exchange between different tools of EDA domain during any phase of design. The specification for SPEF is a part of the 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System. The latest version of SPEF is part of 1481-2019 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) . SPEF is extracted after routing in Place and route stage. This helps in the accurate calculation of IR-drop analysis and other analysis after routing. This file contains the R and C parameters depending on the placement of a tile/block and the routing among the placed cells. (en)
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- 12076 (xsd:nonNegativeInteger)
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- Das Standard Parasitic Exchange Format (SPEF) ist ein Dateiformat für den rechnergestützten Entwurf elektronischer Schaltungen. Mit diesem wird der elektrische Widerstand und die Kapazität sowie die Verzögerungszeit von Verdrahtungselementen beschrieben. Die Daten sind im SPICE-Format abgelegt. Das SPEF ist Teil des Standards IEEE 1481-1999. (de)
- Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Non-ideal wires have parasitic resistance and capacitance that are captured by SPEF. These wires also have inductance that is not included in SPEF. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation. SPEF is the most popular specification for parasitic exchange between different tools of EDA domain during any phase of design. (en)
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- Format Standard Parasitic Exchange (ca)
- Standard Parasitic Exchange Format (de)
- Standard Parasitic Exchange Format (en)
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