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- In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher than static logic but the capacitive loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design. Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. static RAM from dynamic RAM. (en)
- En électronique numérique, les circuits peuvent être ou statiques ou dynamiques. Les circuits dynamiques utilisent des stockages temporaires modélisables par des condensateurs, ce qui n'est pas le cas dans les circuits dits statiques, où le stockage se fait grâce à des circuits bistables, comme les bascules.
* Portail de l’électricité et de l’électronique (fr)
- Динамическая логика (или тактированная логика) — методология разработки комбинационных схем, при которой проектируемая схема работает по тактам. Реализуется, в частности, по технологии КМОП. Применяется при проектировании интегральных схем. (ru)
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- 13215 (xsd:nonNegativeInteger)
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- June 2020 (en)
- September 2021 (en)
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- Citation discusses radiation hardness as pertaining to a specific project, but does not clearly or reliably make or support the claim that this makes fully-static logic families mandatory. (en)
- is this related to High-temperature operating life#Digital toggling factor ? (en)
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- En électronique numérique, les circuits peuvent être ou statiques ou dynamiques. Les circuits dynamiques utilisent des stockages temporaires modélisables par des condensateurs, ce qui n'est pas le cas dans les circuits dits statiques, où le stockage se fait grâce à des circuits bistables, comme les bascules.
* Portail de l’électricité et de l’électronique (fr)
- Динамическая логика (или тактированная логика) — методология разработки комбинационных схем, при которой проектируемая схема работает по тактам. Реализуется, в частности, по технологии КМОП. Применяется при проектировании интегральных схем. (ru)
- In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher than static logic but the capacitive loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to (en)
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- Dynamic logic (digital electronics) (en)
- Circuits statiques et dynamiques (fr)
- Динамическая логика (цифровая электроника) (ru)
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