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"1113554096"^^ . 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"Die Leiterplattenentflechtung ist ein Arbeitsschritt beim Layoutentwurf (kurz: layouten) von elektronischen Leiterplatten. Dabei wird der entworfene elektrische Schaltplan nach dem manuellen oder automatischen Platzieren der Bauelemente auf der Leiterplatte in ein Leiterbahnnetzwerk umgesetzt. Sie wird heute fast ausnahmslos am Computer per Hand oder automatisiert mithilfe eines sogenannten Autorouters durchgef\u00FChrt. CAD-Software zum Leiterplattenentwurf umfasst neben dem Schaltplanentwurf und dessen Simulation oft auch Auto-Platzierer und Autorouter. Damit ein Autorouter sinnvolle Ergebnisse liefern kann, m\u00FCssen ihm zuvor Designregeln vorgegeben werden. Macht man das nicht, sto\u00DFen diese automatischen Funktionen an Grenzen, so dass Leiterbahnen zumindest teilweise manuell verlegt werden m\u00FCssen."@de . . . . . . "Placement is an essential step in electronic design automation \u2014 the portion of the physical design flow that assigns exact locations for various circuit components within the chip's core area. An inferior placement assignment will not only affect the chip's performance but might also make it non-manufacturable by producing excessive wire-length, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Together, the placement and routing steps of IC design are known as place and route. A placer takes a given synthesized circuit netlist together with a technology library and produces a valid placement layout. The layout is optimized according to the aforementioned objectives and ready for cell resizing and buffering \u2014 a step essential for timing and signal integrity satisfaction. Clock-tree synthesis and Routing follow, completing the physical design process. In many cases, parts of, or the entire, physical design flow are iterated a number of times until design closure is achieved. In the case of application-specific integrated circuits, or ASICs, the chip's core layout area comprises a number of fixed height rows, with either some or no space between them. Each row consists of a number of sites which can be occupied by the circuit components. A free site is a site that is not occupied by any component. Circuit components are either standard cells, macro blocks, or I/O pads. Standard cells have a fixed height equal to a row's height, but have variable widths. The width of a cell is an integral number of sites. On the other hand, blocks are typically larger than cells and have variable heights that can stretch a multiple number of rows. Some blocks can have preassigned locations \u2014 say from a previous floorplanning process \u2014 which limit the placer's task to assigning locations for just the cells. In this case, the blocks are typically referred to by fixed blocks. Alternatively, some or all of the blocks may not have preassigned locations. In this case, they have to be placed with the cells in what is commonly referred to as mixed-mode placement. In addition to ASICs, placement retains its prime importance in gate array structures such as field-programmable gate arrays (FPGAs). In FPGAs, placement maps the circuit's subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing."@en . . . . . . . . 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"\u0648\u0636\u0639 \u0627\u0644\u0645\u0643\u0648\u0646\u0627\u062A (\u0627\u0644\u062A\u0635\u0645\u064A\u0645 \u0627\u0644\u0625\u0644\u0643\u062A\u0631\u0648\u0646\u064A)"@ar . . . . . . "9576"^^ . "Placement is an essential step in electronic design automation \u2014 the portion of the physical design flow that assigns exact locations for various circuit components within the chip's core area. An inferior placement assignment will not only affect the chip's performance but might also make it non-manufacturable by producing excessive wire-length, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Together, the placement and routing steps of IC design are known as place and route."@en . . "Die Leiterplattenentflechtung ist ein Arbeitsschritt beim Layoutentwurf (kurz: layouten) von elektronischen Leiterplatten. Dabei wird der entworfene elektrische Schaltplan nach dem manuellen oder automatischen Platzieren der Bauelemente auf der Leiterplatte in ein Leiterbahnnetzwerk umgesetzt. Sie wird heute fast ausnahmslos am Computer per Hand oder automatisiert mithilfe eines sogenannten Autorouters durchgef\u00FChrt."@de . "Leiterplattenentflechtung"@de . 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