This HTML5 document contains 93 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
yago-reshttp://yago-knowledge.org/resource/
dbohttp://dbpedia.org/ontology/
foafhttp://xmlns.com/foaf/0.1/
n9https://global.dbpedia.org/id/
n21http://wilsonminesco.com/6502interrupts/
n15http://sbc.bcstechnology.net/
yagohttp://dbpedia.org/class/yago/
dbthttp://dbpedia.org/resource/Template:
rdfshttp://www.w3.org/2000/01/rdf-schema#
freebasehttp://rdf.freebase.com/ns/
n17https://www.pagetable.com/
n18http://
n22http://dbpedia.org/resource/WDC_65816/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
owlhttp://www.w3.org/2002/07/owl#
n19http://nesdev.parodius.com/
wikipedia-enhttp://en.wikipedia.org/wiki/
dbphttp://dbpedia.org/property/
dbchttp://dbpedia.org/resource/Category:
provhttp://www.w3.org/ns/prov#
xsdhhttp://www.w3.org/2001/XMLSchema#
wikidatahttp://www.wikidata.org/entity/
dbrhttp://dbpedia.org/resource/

Statements

Subject Item
dbr:Interrupts_in_65xx_processors
rdf:type
yago:Microprocessor103760310 yago:SemiconductorDevice104171831 yago:Conductor103088707 yago:Artifact100021939 yago:Wikicat65xxMicroprocessors yago:Device103183080 yago:PhysicalEntity100001930 yago:Chip103020034 yago:Whole100003553 yago:Instrumentality103575240 yago:Object100002684
rdfs:label
Interrupts in 65xx processors
rdfs:comment
The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the BRK instruction. The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor of some type (e.g., a floating point processor).
dcterms:subject
dbc:65xx_microprocessors dbc:Machine_code dbc:Interrupts
dbo:wikiPageID
7938869
dbo:wikiPageRevisionID
1124543849
dbo:wikiPageWikiLink
dbr:Software_interrupt dbr:Microprocessor dbr:Interrupt dbr:Subroutine dbr:Machine_language_monitor dbr:Supervisor_call_instruction dbr:Reentrancy_(computing) dbr:Reset_(computing) dbr:Least_significant_byte dbr:Hardware_interrupt dbr:Programmable_read-only_memory dbr:Segmentation_fault dbr:Stack_pointer dbr:Floating_point_processor dbr:Interrupt_handler dbr:EEPROM dbr:Interrupt_latency dbc:65xx_microprocessors dbr:Binary-coded_decimal dbr:NOP_(code) dbr:65C02 dbr:Logic_level dbc:Machine_code dbr:Program_counter dbr:Random-access_memory dbr:Stack_(data_structure) dbr:Most_significant_byte dbr:WDC_65C02 dbr:EPROM dbr:Machine_cycle dbr:Index_register dbr:Status_register dbr:Maskable_interrupt dbr:Assembly_language dbr:Debug dbr:Coprocessor dbr:Page_fault dbr:Lookup_table dbr:CMOS dbr:Address_bus dbr:Mainframe_computer dbr:Interrupt_service_routine dbr:Opcode dbr:NMOS_logic dbr:Operand dbr:Catatonia dbr:Software_bug dbr:MOS_Technology dbc:Interrupts dbr:MOS_Technology_6502 n22:65802 dbr:Western_Design_Center dbr:CSG_65CE02 dbr:Firmware dbr:Non-maskable_interrupt dbr:Accumulator_(computing) dbr:Bitwise_operation
dbo:wikiPageExternalLink
n15:65c816interrupts.html n17:%3Fp=410 n18:www.6502.org n19:the%20'B'%20flag%20&%20BRK%20instruction.txt%7Ctitle=6502 n21:index.html
owl:sameAs
freebase:m.026kt85 n9:4nr1B yago-res:Interrupts_in_65xx_processors wikidata:Q6056666
dbp:wikiPageUsesTemplate
dbt:Refn dbt:Mono dbt:MOS_CPU dbt:Cite_web dbt:Redirect
dbo:abstract
The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the BRK instruction. The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor of some type (e.g., a floating point processor).
prov:wasDerivedFrom
wikipedia-en:Interrupts_in_65xx_processors?oldid=1124543849&ns=0
dbo:wikiPageLength
29680
foaf:isPrimaryTopicOf
wikipedia-en:Interrupts_in_65xx_processors