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About: Verilator     Goto   Sponge   NotDistinct   Permalink

An Entity of Type : yago:Software106566077, within Data Space : dbpedia.org associated with source document(s)

Type: Thingsoftwareschema:CreativeWorkworkwikidata:Q386724Softwareyago:Abstraction100002137yago:Code106355894yago:CodingSystem106353757yago:Communication100033020yago:Writing106359877yago:WrittenCommunication106349220yago:Software106566077 New Facet based on Instances of this Class

Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.