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Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University. It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip. The boards designed at Stanford implemented a directory-based cache coherence protocol allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency. Because Stanford DASH was the first operational machine to include scalable cac

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  • Stanford DASH
  • Stanford DASH
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  • Stanford DASH fue un multiprocesador coherente de caché desarrollado a fines de la década de 1980 por un grupo dirigido por Anoop Gupta, John L. Hennessy, Mark Horowitz y Monica S. Lam en la Universidad de Stanford.​ Se basó en agregar un par de tableros de directorio diseñados en Stanford a 16 máquinas SGI IRIS 4D Power Series y luego cablear los sistemas en una topología de malla usando una versión modificada de Stanford del Torus Routing Chip.​ Las placas diseñadas en Stanford implementaron un protocolo de coherencia de caché basado en directorio,​ permitiendo al Stanford DASH admitir memoria compartida distribuida para hasta 64 procesadores. Stanford DASH también se destacó por apoyar y ayudar a formalizar modelos de consistencia de memoria débil, incluida la consistencia de lanzamient
  • Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University. It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip. The boards designed at Stanford implemented a directory-based cache coherence protocol allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency. Because Stanford DASH was the first operational machine to include scalable cac
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  • Stanford DASH fue un multiprocesador coherente de caché desarrollado a fines de la década de 1980 por un grupo dirigido por Anoop Gupta, John L. Hennessy, Mark Horowitz y Monica S. Lam en la Universidad de Stanford.​ Se basó en agregar un par de tableros de directorio diseñados en Stanford a 16 máquinas SGI IRIS 4D Power Series y luego cablear los sistemas en una topología de malla usando una versión modificada de Stanford del Torus Routing Chip.​ Las placas diseñadas en Stanford implementaron un protocolo de coherencia de caché basado en directorio,​ permitiendo al Stanford DASH admitir memoria compartida distribuida para hasta 64 procesadores. Stanford DASH también se destacó por apoyar y ayudar a formalizar modelos de consistencia de memoria débil, incluida la consistencia de lanzamiento.​ Debido a que Stanford DASH fue la primera máquina operativa que incluyó una coherencia de caché escalable,​ influyó en la investigación informática posterior, así como en el SGI Origin 2000 disponible comercialmente. Stanford DASH está incluido en la retrospectiva del 25 aniversario de trabajos seleccionados del Simposio Internacional sobre Arquitectura de Computadores​ y varios libros de informática,​​​​​ han sido simulados por la Universidad de Edimburgo,​ y se utiliza como estudio de caso en las clases contemporáneas de informática.​​
  • Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University. It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip. The boards designed at Stanford implemented a directory-based cache coherence protocol allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency. Because Stanford DASH was the first operational machine to include scalable cache coherence, it influenced subsequent computer science research as well as the commercially available SGI Origin 2000. Stanford DASH is included in the 25th anniversary retrospective of selected papers from the International Symposium on Computer Architecture and several computer science books, has been simulated by the University of Edinburgh, and is used as a case study in contemporary computer science classes.
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