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About: R10000     Goto   Sponge   NotDistinct   Permalink

An Entity of Type : yago:Whole100003553, within Data Space : dbpedia.org associated with source document(s)

Type: softwareyago:WikicatMIPSMicroprocessorsyago:WikicatMicroprocessorsyago:Artifact100021939yago:Chip103020034yago:Conductor103088707yago:Device103183080yago:Instrumentality103575240yago:Microprocessor103760310yago:Object100002684yago:PhysicalEntity100001930yago:SemiconductorDevice104171831yago:Whole100003553 New Facet based on Instances of this Class

The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.