About: Computation of cyclic redundancy checks

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Computation of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. In practice, it resembles long division of the binary message string, with a fixed number of zeroes appended, by the "generator polynomial" string except that exclusive or operations replace subtractions. Division of this type is efficiently realised in hardware by a modified shift register, and in software by a series of equivalent algorithms, starting with simple code close to the mathematics and becoming faster (and arguably more obfuscated) through byte-wise parallelism and space–time tradeoffs.

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rdfs:label	Computation of cyclic redundancy checks (en)
rdfs:comment	Computation of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. In practice, it resembles long division of the binary message string, with a fixed number of zeroes appended, by the "generator polynomial" string except that exclusive or operations replace subtractions. Division of this type is efficiently realised in hardware by a modified shift register, and in software by a series of equivalent algorithms, starting with simple code close to the mathematics and becoming faster (and arguably more obfuscated) through byte-wise parallelism and space–time tradeoffs. (en)
foaf:depiction
dcterms:subject	Cyclic redundancy checks Articles with example pseudocode Finite fields
Wikipage page ID	15378076 (xsd:integer)
Wikipage revision ID	1110767272 (xsd:integer)
Link from a Wikipage to another Wikipage	8B/10B encoding Propagation delay Binary code Algorithm Cyclic redundancy check List of hash functions Commutative Object (computer science) Shift register Endianness GitHub Most significant bit Long division Cyclic redundancy checks ZIP (file format) Mathematics of cyclic redundancy checks Articles with example pseudocode Byte CCITT Adler-32 Space–time tradeoff ASCII Error correcting code Exclusive OR Exclusive or FDDI Floppy disk Object composition Hexadecimal Asynchronous serial communication Finite fields Least significant bit Bit-serial architecture Burst error CRC-based framing Portable Network Graphics Microcontrollers Associative Carry (arithmetic) RS-232 XMODEM Lookup table Serial communication Serial port Software Ethernet IEEE 802 Fletcher's checksum Pseudocode Superscalar Image format Archive formats Hardware (computer) Parallel transmission Parallelism (computing) Parity (telecommunication) Hard drive Constructor (computer science) Obfuscated code
Link from a Wikipage to an external page	http://pages.pathcom.com/~vadco/crc.html https://github.com/lizardfs/lizardfs/tree/master/external/crcutil-1.0
sameAs	Computation of cyclic redundancy checks Computation of cyclic redundancy checks Computation of cyclic redundancy checks Computation of cyclic redundancy checks
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thumbnail	wiki-commons:Special:FilePath/CRC8-gen.gif?width=300
date	August 2017 (en)
section	7 (xsd:integer)
has abstract	Computation of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. In practice, it resembles long division of the binary message string, with a fixed number of zeroes appended, by the "generator polynomial" string except that exclusive or operations replace subtractions. Division of this type is efficiently realised in hardware by a modified shift register, and in software by a series of equivalent algorithms, starting with simple code close to the mathematics and becoming faster (and arguably more obfuscated) through byte-wise parallelism and space–time tradeoffs. Various CRC standards extend the polynomial division algorithm by specifying an initial shift register value, a final Exclusive-Or step and, most critically, a bit ordering (endianness). As a result, the code seen in practice deviates confusingly from "pure" division, and the register may shift left or right. (en)
prov:wasDerivedFrom	wikipedia-en:Computation_of_cyclic_redundancy_checks?oldid=1110767272&ns=0
page length (characters) of wiki page	47544 (xsd:nonNegativeInteger)

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