. . . . . "5400"^^ . . . . "The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs."@en . . "7024370"^^ . . . . . . "The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs."@en . . . . . . "\u65F6\u5E8F\u6536\u655B"@zh . . . . . . "\u65F6\u5E8F\u6536\u655B\uFF08\u82F1\u8A9E\uFF1ATiming closure\uFF09\u662F\u73B0\u573A\u53EF\u7F16\u7A0B\u903B\u8F91\u95E8\u9635\u5217\u3001\u7279\u6B8A\u61C9\u7528\u7A4D\u9AD4\u96FB\u8DEF\u7B49\u96C6\u6210\u7535\u8DEF\u8BBE\u8BA1\u8FC7\u7A0B\u4E2D\uFF0C\u8C03\u6574\u3001\u4FEE\u6539\u8BBE\u8BA1\uFF0C\u4ECE\u800C\u4F7F\u5F97\u6240\u8BBE\u8BA1\u7684\u7535\u8DEF\u6EE1\u8DB3\u65F6\u5E8F\u8981\u6C42\u7684\u8FC7\u7A0B\u3002\u4E3A\u4E86\u5B8C\u6210\u4E0A\u8FF0\u8FC7\u7A0B\uFF0C\u5DE5\u7A0B\u5E08\u5E38\u5E38\u9700\u8981\u5728\u7535\u5B50\u8BBE\u8BA1\u81EA\u52A8\u5316\u5DE5\u5177\u8F85\u52A9\u4E0B\u5DE5\u4F5C\u3002\u201C\u65F6\u5E8F\u6536\u655B\u201D\u4E00\u8BCD\u6709\u65F6\u4E5F\u7528\u4E8E\u8868\u8FBE\u8FD9\u4E9B\u8981\u6C42\u6700\u7EC8\u88AB\u6EE1\u8DB3\u7684\u72B6\u6001\u3002"@zh . "1122754300"^^ . . . . . "\u65F6\u5E8F\u6536\u655B\uFF08\u82F1\u8A9E\uFF1ATiming closure\uFF09\u662F\u73B0\u573A\u53EF\u7F16\u7A0B\u903B\u8F91\u95E8\u9635\u5217\u3001\u7279\u6B8A\u61C9\u7528\u7A4D\u9AD4\u96FB\u8DEF\u7B49\u96C6\u6210\u7535\u8DEF\u8BBE\u8BA1\u8FC7\u7A0B\u4E2D\uFF0C\u8C03\u6574\u3001\u4FEE\u6539\u8BBE\u8BA1\uFF0C\u4ECE\u800C\u4F7F\u5F97\u6240\u8BBE\u8BA1\u7684\u7535\u8DEF\u6EE1\u8DB3\u65F6\u5E8F\u8981\u6C42\u7684\u8FC7\u7A0B\u3002\u4E3A\u4E86\u5B8C\u6210\u4E0A\u8FF0\u8FC7\u7A0B\uFF0C\u5DE5\u7A0B\u5E08\u5E38\u5E38\u9700\u8981\u5728\u7535\u5B50\u8BBE\u8BA1\u81EA\u52A8\u5316\u5DE5\u5177\u8F85\u52A9\u4E0B\u5DE5\u4F5C\u3002\u201C\u65F6\u5E8F\u6536\u655B\u201D\u4E00\u8BCD\u6709\u65F6\u4E5F\u7528\u4E8E\u8868\u8FBE\u8FD9\u4E9B\u8981\u6C42\u6700\u7EC8\u88AB\u6EE1\u8DB3\u7684\u72B6\u6001\u3002"@zh . . "Timing closure"@en . . . . . . . .