"Back side bus (BSB) \u2014 \u0448\u0438\u043D\u0430 \u043A\u044D\u0448-\u043F\u0430\u043C\u044F\u0442\u0438 \u0432\u0442\u043E\u0440\u043E\u0433\u043E \u0443\u0440\u043E\u0432\u043D\u044F \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430\u0445 \u0441 \u0434\u0432\u043E\u0439\u043D\u043E\u0439 \u043D\u0435\u0437\u0430\u0432\u0438\u0441\u0438\u043C\u043E\u0439 \u0448\u0438\u043D\u043E\u0439 (\u0430\u043D\u0433\u043B. DIB \u2014 dual independed bus). \u0414\u043B\u044F \u0441\u0432\u044F\u0437\u0438 \u0441 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440\u043E\u043C \u043F\u0430\u043C\u044F\u0442\u0438 \u043F\u0440\u0435\u0434\u043D\u0430\u0437\u043D\u0430\u0447\u0435\u043D\u0430 FSB (front side bus), \u0440\u0430\u0431\u043E\u0442\u0430\u044E\u0449\u0430\u044F \u0432 \u043A\u0430\u0447\u0435\u0441\u0442\u0432\u0435 \u043C\u0430\u0433\u0438\u0441\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u0433\u043E \u043A\u0430\u043D\u0430\u043B\u0430 \u043C\u0435\u0436\u0434\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u043C \u0438 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C. \u041A \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430\u043C, \u0438\u043C\u0435\u044E\u0449\u0438\u043C \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u0443 DIB, \u043E\u0442\u043D\u043E\u0441\u044F\u0442\u0441\u044F:"@ru . "\u540E\u7AEF\u603B\u7EBF\uFF08BSB\uFF0CBack Side Bus\uFF09\uFF1A\u5E26\u6709L2\u548CL3\u7F13\u5B58\uFF08Cache\uFF09\u7684\u8BA1\u7B97\u673A\u4E2D\uFF0C\u8D1F\u8D23\u4E2D\u592E\u5904\u7406\u5668\u548C\uFF08\u7ECF\u5E38\u4E3A\u7B2C\u4E8C\u7EA7\u7F13\u5B58\uFF09\u4E4B\u95F4\u7684\u6570\u636E\u4F20\u9012\u7684\u6570\u636E\u901A\u9053\u3002\u540E\u7AEF\u603B\u7EBF\u4F20\u8F93\u901F\u7387\u603B\u662F\u9AD8\u4E8E\u524D\u7AEF\u603B\u7EBF\u3002\u7528\u4E8E\u5904\u7406\u7F13\u5B58\u6570\u636E\u7684\u540E\u7AEF\u603B\u7EBF\u5B9E\u9645\u4E0A\u662F\u4EE5CPU\u65F6\u949F\u901F\u5EA6\u8FD0\u884C\u3002\u5728\u572890\u5E74\u4EE3\u4E2D\u671F\uFF0C\u540E\u7AEF\u603B\u7EBF\u66FE\u662F\u4FDD\u6301\u6570\u636E\u79FB\u52A8\u7684\u91CD\u8981\u8DEF\u5F84\u3002Intel\u516C\u53F8\u7684Pentium II\u548CPentium Pro\u90FD\u4F7F\u7528\u6240\u8C13\u7684\u82AF\u7247\u5916\u7F13\u5B58\uFF0C\u4E0E\u4FDD\u5B58\u5728\u4F20\u7EDF\u5185\u5B58\u4E2D\u7684\u6570\u636E\u76F8\u6BD4\uFF0C\u8FD9\u7C7B\u7F13\u5B58\u5C06\u7ECF\u5E38\u4F7F\u7528\u7684\u6570\u636E\u9760\u8FD1\uFF08\u5728\u8BBF\u95EE\u6570\u636E\u6240\u9700\u7684\u8DDD\u79BB\u548C\u65F6\u95F4\u4E0A\uFF09\u4E3B\u5904\u7406\u5355\u5143\u4FDD\u5B58\u3002\u8FDE\u7EBF\u5C06CPU\u8FDE\u63A5\u5230\u7B2C\u4E8C\u7EA7\uFF08L2\uFF09\u7F13\u5B58\u8D44\u6E90\u5E76\u4EE5CPU\u65F6\u949F\u901F\u5EA6\u5728CPU\u4E0EL2\u7F13\u5B58\u4E4B\u95F4\u4EA4\u6362\u6570\u636E\u3002AMD\u516C\u53F8\u6B64\u540E\u4E5F\u5F00\u59CB\u91C7\u7528\u540C\u6837\u7684\u6218\u7565\u3002"@zh . . . . "Back-side bus (BSB) \u2014 \u0448\u0438\u043D\u0430 \u043A\u0435\u0448-\u043F\u0430\u043C'\u044F\u0442\u0456 \u0434\u0440\u0443\u0433\u043E\u0433\u043E \u0440\u0456\u0432\u043D\u044F \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430\u0445 \u0437 \u043F\u043E\u0434\u0432\u0456\u0439\u043D\u043E\u044E \u043D\u0435\u0437\u0430\u043B\u0435\u0436\u043D\u043E\u044E \u0448\u0438\u043D\u043E\u044E (\u0430\u043D\u0433\u043B. DIB - dual independed bus). \u0414\u043B\u044F \u0437\u0432'\u044F\u0437\u043A\u0443 \u0437 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440\u043E\u043C \u043F\u0430\u043C'\u044F\u0442\u0456 \u043F\u0440\u0438\u0437\u043D\u0430\u0447\u0435\u043D\u0430 FSB (front-side bus), \u0449\u043E \u043F\u0440\u0430\u0446\u044E\u0454 \u044F\u043A \u043C\u0430\u0433\u0456\u0441\u0442\u0440\u0430\u043B\u044C\u043D\u0438\u0439 \u043A\u0430\u043D\u0430\u043B \u043C\u0456\u0436 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u043E\u043C \u0456 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C. \u0414\u043E \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0456\u0432 \u043D\u0430 \u0430\u0440\u0445\u0456\u0442\u0435\u043A\u0442\u0443\u0440\u0456 DIB \u0432\u0456\u0434\u043D\u043E\u0441\u044F\u0442\u044C\u0441\u044F: \u0442\u0430 \u0456\u043D."@uk . "\u5F8C\u7AEF\u532F\u6D41\u6392"@zh . . . . . . "Na arquitetura de microprocessadores, o Backside bus (ou barramento traseiro) era um barramento de computador usado nas primeiras plataformas Intel para conectar a CPU \u00E0 mem\u00F3ria cache da CPU - geralmente na cache L2 nos processadores que o t\u00EAm embutido. Se um projeto o utiliza junto com um barramento frontal, \u00E9 considerado parte de uma arquitetura de barramento duplo ou, na terminologia da Intel, arquitetura Dual Independent Bus. A arquitetura de backside bus foi descontinuada quando os processadores mais novos come\u00E7aram a incorporar cache L2."@pt . "En las computadoras personales de la segunda mitad de la d\u00E9cada de 1990, el Back Side Bus (BSB, literalmente \u201Cbus trasero\u201D, en contraposici\u00F3n al frontal o FSB) se refiere a la conexi\u00F3n entre un microprocesador y su memoria cache externa, en particular y com\u00FAnmente la de segundo nivel o L2 (en ingl\u00E9s, Level 2).\u200B Dado que el concepto de BSB vino a complementar al de FSB, las computadoras modernas utilizan una \u201Carquitectura de bus dual\u201D o, en la nomenclatura de Intel, Dual Independent Bus (DIB)..\u200B"@es . . "Back-side bus"@en . . . . "Back side bus"@ru . . . . . . "Backside bus"@pt . "Na arquitetura de microprocessadores, o Backside bus (ou barramento traseiro) era um barramento de computador usado nas primeiras plataformas Intel para conectar a CPU \u00E0 mem\u00F3ria cache da CPU - geralmente na cache L2 nos processadores que o t\u00EAm embutido. Se um projeto o utiliza junto com um barramento frontal, \u00E9 considerado parte de uma arquitetura de barramento duplo ou, na terminologia da Intel, arquitetura Dual Independent Bus. A arquitetura de backside bus foi descontinuada quando os processadores mais novos come\u00E7aram a incorporar cache L2."@pt . . "339045"^^ . "4108"^^ . . "In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB) architecture. The back-side bus architecture evolved when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache, but Intel continued to refer to the Dual Independent Bus till the end of Pentium III."@en . . . "En las computadoras personales de la segunda mitad de la d\u00E9cada de 1990, el Back Side Bus (BSB, literalmente \u201Cbus trasero\u201D, en contraposici\u00F3n al frontal o FSB) se refiere a la conexi\u00F3n entre un microprocesador y su memoria cache externa, en particular y com\u00FAnmente la de segundo nivel o L2 (en ingl\u00E9s, Level 2).\u200B Dado que el concepto de BSB vino a complementar al de FSB, las computadoras modernas utilizan una \u201Carquitectura de bus dual\u201D o, en la nomenclatura de Intel, Dual Independent Bus (DIB)..\u200B"@es . . . . . . "Back side bus (BSB) \u2014 \u0448\u0438\u043D\u0430 \u043A\u044D\u0448-\u043F\u0430\u043C\u044F\u0442\u0438 \u0432\u0442\u043E\u0440\u043E\u0433\u043E \u0443\u0440\u043E\u0432\u043D\u044F \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430\u0445 \u0441 \u0434\u0432\u043E\u0439\u043D\u043E\u0439 \u043D\u0435\u0437\u0430\u0432\u0438\u0441\u0438\u043C\u043E\u0439 \u0448\u0438\u043D\u043E\u0439 (\u0430\u043D\u0433\u043B. DIB \u2014 dual independed bus). \u0414\u043B\u044F \u0441\u0432\u044F\u0437\u0438 \u0441 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440\u043E\u043C \u043F\u0430\u043C\u044F\u0442\u0438 \u043F\u0440\u0435\u0434\u043D\u0430\u0437\u043D\u0430\u0447\u0435\u043D\u0430 FSB (front side bus), \u0440\u0430\u0431\u043E\u0442\u0430\u044E\u0449\u0430\u044F \u0432 \u043A\u0430\u0447\u0435\u0441\u0442\u0432\u0435 \u043C\u0430\u0433\u0438\u0441\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u0433\u043E \u043A\u0430\u043D\u0430\u043B\u0430 \u043C\u0435\u0436\u0434\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u043C \u0438 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C. \u041A \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430\u043C, \u0438\u043C\u0435\u044E\u0449\u0438\u043C \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u0443 DIB, \u043E\u0442\u043D\u043E\u0441\u044F\u0442\u0441\u044F: \n* Intel Pentium Pro \u2014 64-\u0431\u0438\u0442\u043D\u0430\u044F BSB; \n* Intel Pentium II \u2014 64-\u0431\u0438\u0442\u043D\u0430\u044F BSB (\u0432\u043D\u0435\u0448\u043D\u0438\u0439 \u043A\u044D\u0448 L2); \n* Intel Pentium III \u2014 64 \u0431\u0438\u0442 + 8 \u0431\u0438\u0442 ECC (\u0432\u043D\u0435\u0448\u043D\u0438\u0439 \u043A\u044D\u0448 L2) \u0438\u043B\u0438 256 \u0431\u0438\u0442 + 32 \u0431\u0438\u0442 ECC; \n* Intel Pentium 4 \u2014 256 \u0431\u0438\u0442 + 32 \u0431\u0438\u0442 ECC; \n* Intel Core \u2014 256 \u0431\u0438\u0442 + 32 \u0431\u0438\u0442 ECC; \n* AMD Athlon \u2014 64 \u0431\u0438\u0442 + 8 \u0431\u0438\u0442 ECC: \n* AMD Athlon 64 \u2014 128 \u0431\u0438\u0442 + 16 \u0431\u0438\u0442 ECC (\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 \u0441\u0435\u043C\u0435\u0439\u0441\u0442\u0432\u0430 K8 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440 \u043F\u0430\u043C\u044F\u0442\u0438 \u0432\u0441\u0442\u0440\u043E\u0435\u043D \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440, \u0441\u0432\u044F\u0437\u044C \u0441 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C \u043E\u0441\u0443\u0449\u0435\u0441\u0442\u0432\u043B\u044F\u0435\u0442\u0441\u044F \u043F\u043E \u0448\u0438\u043D\u0435 HyperTransport); \n* \u0438 \u0434\u0440."@ru . . . "What is \"on-chip FSB\" and how does it differ from \"off-chip FSB\"? Aren't all FSBs made for off-chip communicatio?"@en . . "\u540E\u7AEF\u603B\u7EBF\uFF08BSB\uFF0CBack Side Bus\uFF09\uFF1A\u5E26\u6709L2\u548CL3\u7F13\u5B58\uFF08Cache\uFF09\u7684\u8BA1\u7B97\u673A\u4E2D\uFF0C\u8D1F\u8D23\u4E2D\u592E\u5904\u7406\u5668\u548C\uFF08\u7ECF\u5E38\u4E3A\u7B2C\u4E8C\u7EA7\u7F13\u5B58\uFF09\u4E4B\u95F4\u7684\u6570\u636E\u4F20\u9012\u7684\u6570\u636E\u901A\u9053\u3002\u540E\u7AEF\u603B\u7EBF\u4F20\u8F93\u901F\u7387\u603B\u662F\u9AD8\u4E8E\u524D\u7AEF\u603B\u7EBF\u3002\u7528\u4E8E\u5904\u7406\u7F13\u5B58\u6570\u636E\u7684\u540E\u7AEF\u603B\u7EBF\u5B9E\u9645\u4E0A\u662F\u4EE5CPU\u65F6\u949F\u901F\u5EA6\u8FD0\u884C\u3002\u5728\u572890\u5E74\u4EE3\u4E2D\u671F\uFF0C\u540E\u7AEF\u603B\u7EBF\u66FE\u662F\u4FDD\u6301\u6570\u636E\u79FB\u52A8\u7684\u91CD\u8981\u8DEF\u5F84\u3002Intel\u516C\u53F8\u7684Pentium II\u548CPentium Pro\u90FD\u4F7F\u7528\u6240\u8C13\u7684\u82AF\u7247\u5916\u7F13\u5B58\uFF0C\u4E0E\u4FDD\u5B58\u5728\u4F20\u7EDF\u5185\u5B58\u4E2D\u7684\u6570\u636E\u76F8\u6BD4\uFF0C\u8FD9\u7C7B\u7F13\u5B58\u5C06\u7ECF\u5E38\u4F7F\u7528\u7684\u6570\u636E\u9760\u8FD1\uFF08\u5728\u8BBF\u95EE\u6570\u636E\u6240\u9700\u7684\u8DDD\u79BB\u548C\u65F6\u95F4\u4E0A\uFF09\u4E3B\u5904\u7406\u5355\u5143\u4FDD\u5B58\u3002\u8FDE\u7EBF\u5C06CPU\u8FDE\u63A5\u5230\u7B2C\u4E8C\u7EA7\uFF08L2\uFF09\u7F13\u5B58\u8D44\u6E90\u5E76\u4EE5CPU\u65F6\u949F\u901F\u5EA6\u5728CPU\u4E0EL2\u7F13\u5B58\u4E4B\u95F4\u4EA4\u6362\u6570\u636E\u3002AMD\u516C\u53F8\u6B64\u540E\u4E5F\u5F00\u59CB\u91C7\u7528\u540C\u6837\u7684\u6218\u7565\u3002"@zh . . . . . . . "Bus trasero"@es . . "1099435689"^^ . . . . . . . . "July 2022"@en . . . . . . . . . . . . . . "In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB) architecture. The back-side bus architecture evolved when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache, but Intel continued to refer to the Dual Independent Bus till the end of Pentium III."@en . "Back-side bus"@uk . "Back-side bus (BSB) \u2014 \u0448\u0438\u043D\u0430 \u043A\u0435\u0448-\u043F\u0430\u043C'\u044F\u0442\u0456 \u0434\u0440\u0443\u0433\u043E\u0433\u043E \u0440\u0456\u0432\u043D\u044F \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430\u0445 \u0437 \u043F\u043E\u0434\u0432\u0456\u0439\u043D\u043E\u044E \u043D\u0435\u0437\u0430\u043B\u0435\u0436\u043D\u043E\u044E \u0448\u0438\u043D\u043E\u044E (\u0430\u043D\u0433\u043B. DIB - dual independed bus). \u0414\u043B\u044F \u0437\u0432'\u044F\u0437\u043A\u0443 \u0437 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440\u043E\u043C \u043F\u0430\u043C'\u044F\u0442\u0456 \u043F\u0440\u0438\u0437\u043D\u0430\u0447\u0435\u043D\u0430 FSB (front-side bus), \u0449\u043E \u043F\u0440\u0430\u0446\u044E\u0454 \u044F\u043A \u043C\u0430\u0433\u0456\u0441\u0442\u0440\u0430\u043B\u044C\u043D\u0438\u0439 \u043A\u0430\u043D\u0430\u043B \u043C\u0456\u0436 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u043E\u043C \u0456 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C. \u0414\u043E \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0456\u0432 \u043D\u0430 \u0430\u0440\u0445\u0456\u0442\u0435\u043A\u0442\u0443\u0440\u0456 DIB \u0432\u0456\u0434\u043D\u043E\u0441\u044F\u0442\u044C\u0441\u044F: \n* Intel Pentium Pro \u2014 64-\u0431\u0456\u0442\u043D\u0430 BSB; \n* Intel Pentium II \u2014 64-\u0431\u0456\u0442\u043D\u0430 BSB (\u0437\u043E\u0432\u043D\u0456\u0448\u043D\u0456\u0439 \u043A\u0435\u0448 L2); \n* Intel Pentium III \u2014 64 \u0431\u0456\u0442 + 8 \u0431\u0456\u0442 ECC (\u0437\u043E\u0432\u043D\u0456\u0448\u043D\u0456\u0439 \u043A\u0435\u0448 L2) \u0430\u0431\u043E 256 \u0431\u0456\u0442 + 32 \u0431\u0456\u0442 ECC; \n* Intel Pentium 4 \u2014 256 \u0431\u0456\u0442 + 32 \u0431\u0456\u0442 ECC; \n* Intel Core \u2014 256 \u0431\u0456\u0442 + 32 \u0431\u0456\u0442 ECC; \n* AMD Athlon \u2014 64 \u0431\u0456\u0442 + 8 \u0431\u0456\u0442 ECC: \n* AMD Athlon 64 \u2014 128 \u0431\u0456\u0442 + 16 \u0431\u0456\u0442 ECC (\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0456\u0432 \u0441\u0456\u043C\u0435\u0439\u0441\u0442\u0432\u0430 K8 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440 \u043F\u0430\u043C'\u044F\u0442\u0456 \u0432\u0431\u0443\u0434\u043E\u0432\u0430\u043D\u0438\u0439 \u0432 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440, \u0437\u0432'\u044F\u0437\u043E\u043A \u0437 \u0447\u0438\u043F\u0441\u0435\u0442\u043E\u043C \u0437\u0434\u0456\u0439\u0441\u043D\u044E\u0454\u0442\u044C\u0441\u044F \u043F\u043E \u0448\u0438\u043D\u0456 HyperTransport); \u0442\u0430 \u0456\u043D."@uk . . . .