About: Timing closure

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The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs.

Attributes	Values
rdf:type	Election
rdfs:label	Timing closure (en) 时序收敛 (zh)
rdfs:comment	The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs. (en) 时序收敛（英語：Timing closure）是现场可编程逻辑门阵列、特殊應用積體電路等集成电路设计过程中，调整、修改设计，从而使得所设计的电路满足时序要求的过程。为了完成上述过程，工程师常常需要在电子设计自动化工具辅助下工作。“时序收敛”一词有时也用于表达这些要求最终被满足的状态。 (zh)
dcterms:subject	Timing in electronic circuits
Wikipage page ID	7024370 (xsd:integer)
Wikipage revision ID	1122754300 (xsd:integer)
Link from a Wikipage to another Wikipage	Electronic design automation Electronic engineering Design closure Design flow (EDA) Integrated circuit design Timing in electronic circuits Machine learning Clock signal Placement (EDA) Logic synthesis Synchronous circuit Asynchronous circuit Static timing analysis Very Large Scale Integration Sequential logic Routing (EDA) Physical timing closure
Link from a Wikipage to an external page	http://phy-tc.com/docs_timingclosure.html https://www.plunify.com/en/intime/ https://web.archive.org/web/20070206065723/http:/www.synopsys.com/products/iccompiler/iccompiler.html https://web.archive.org/web/20070228233817/http:/www.synopsys.com/products/logic/design_compiler.html http://www.cadence.com/products/digital_ic/rtl_compiler/index.aspx http://www.cadence.com/products/digital_ic/soc_encounter/index.aspx http://www.magma-da.com/Pages/BlastCreate.html http://www.magma-da.com/Pages/blastfusion.html
sameAs	Timing closure Timing closure Timing closure Timing closure
dbp:wikiPageUsesTemplate	dbt:Notes dbt:Technical
has abstract	The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (AND, OR, NOT, NAND, NOR, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs. (en) 时序收敛（英語：Timing closure）是现场可编程逻辑门阵列、特殊應用積體電路等集成电路设计过程中，调整、修改设计，从而使得所设计的电路满足时序要求的过程。为了完成上述过程，工程师常常需要在电子设计自动化工具辅助下工作。“时序收敛”一词有时也用于表达这些要求最终被满足的状态。 (zh)
gold:hypernym	Process
prov:wasDerivedFrom	wikipedia-en:Timing_closure?oldid=1122754300&ns=0
page length (characters) of wiki page	5400 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Timing_closure
is Link from a Wikipage to another Wikipage of	Design closure Integrated circuit design Computer-aided design Computer engineering compendium Jason Cong Arteris Timing Closure Signoff (electronic design automation) Standard Parasitic Exchange Format Physical timing closure Timing simulation
is Wikipage redirect of	Timing Closure Physical timing closure Timing simulation
is foaf:primaryTopic of	wikipedia-en:Timing_closure

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