About: Placement (EDA)     Goto   Sponge   NotDistinct   Permalink

An Entity of Type : yago:Whole100003553, within Data Space : dbpedia.org associated with source document(s)
QRcode icon
http://dbpedia.org/describe/?url=http%3A%2F%2Fdbpedia.org%2Fresource%2FPlacement_%28EDA%29

Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area. An inferior placement assignment will not only affect thechip's performance but might also make it nonmanufacturable by producing excessive wirelength, whichis beyond available routing resources. Consequently, a placer must perform the assignment while optimizinga number of objectives to ensure that a circuit meets its performance demands. Typical placementobjectives include

AttributesValues
rdf:type
rdfs:label
  • Leiterplattenentflechtung
  • Placement (EDA)
  • 布局 (集成电路)
rdfs:comment
  • 布局(英语:placement)是电子设计自动化中的一个重要步骤,它是将电路元件安置在指定面积芯片上物理设计流程。如果电路的布局完成地不好,那么集成电路芯片的性能将会下降,而且会因为连线情况不够优化(对连线的配置称为布线),制造效率也会降低。因此,电路的布局人员必须考虑到对多个参数的优化,以使电路能够符合预定的性能要求。
  • Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area. An inferior placement assignment will not only affect thechip's performance but might also make it nonmanufacturable by producing excessive wirelength, whichis beyond available routing resources. Consequently, a placer must perform the assignment while optimizinga number of objectives to ensure that a circuit meets its performance demands. Typical placementobjectives include
  • Die Leiterplattenentflechtung ist ein Arbeitsschritt beim Layoutentwurf (kurz: layouten) von elektronischen Leiterplatten. Dabei wird der entworfene elektrische Schaltplan nach dem manuellen oder automatischen Platzieren (vgl. Autoplacer) der benötigten Bauelemente auf der Leiterplatte in ein Leiterbahnnetzwerk umgesetzt. Sie wird heute fast ausnahmslos am Computer per Hand oder automatisiert mithilfe eines sogenannten Autorouters durchgeführt.
sameAs
dct:subject
Wikipage page ID
Wikipage revision ID
Link from a Wikipage to another Wikipage
Link from a Wikipage to an external page
foaf:isPrimaryTopicOf
prov:wasDerivedFrom
has abstract
  • Die Leiterplattenentflechtung ist ein Arbeitsschritt beim Layoutentwurf (kurz: layouten) von elektronischen Leiterplatten. Dabei wird der entworfene elektrische Schaltplan nach dem manuellen oder automatischen Platzieren (vgl. Autoplacer) der benötigten Bauelemente auf der Leiterplatte in ein Leiterbahnnetzwerk umgesetzt. Sie wird heute fast ausnahmslos am Computer per Hand oder automatisiert mithilfe eines sogenannten Autorouters durchgeführt. CAD-Software zum Leiterplattenentwurf umfasst neben dem Schaltplanentwurf und dessen Simulation oft auch Auto-Platzierer und Autorouter. Damit ein Autorouter sinnvolle Ergebnisse liefern kann, müssen ihm zuvor Designregeln vorgegeben werden. Macht man das nicht, stoßen diese automatischen Funktionen an Grenzen, so dass Leiterbahnen zumindest teilweise manuell verlegt werden müssen.
  • Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area. An inferior placement assignment will not only affect thechip's performance but might also make it nonmanufacturable by producing excessive wirelength, whichis beyond available routing resources. Consequently, a placer must perform the assignment while optimizinga number of objectives to ensure that a circuit meets its performance demands. Typical placementobjectives include * Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength (This assumes long wires have additional buffering inserted; all modern design flows do this.) * Timing: The clock cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay. * Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours, or make it impossible to complete all routes. * Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients. * A secondary objective is placement runtime minimization.
  • 布局(英语:placement)是电子设计自动化中的一个重要步骤,它是将电路元件安置在指定面积芯片上物理设计流程。如果电路的布局完成地不好,那么集成电路芯片的性能将会下降,而且会因为连线情况不够优化(对连线的配置称为布线),制造效率也会降低。因此,电路的布局人员必须考虑到对多个参数的优化,以使电路能够符合预定的性能要求。
http://purl.org/voc/vrank#hasRank
http://purl.org/li...ics/gold/hypernym
is Link from a Wikipage to another Wikipage of
is Wikipage redirect of
is Wikipage disambiguates of
is foaf:primaryTopic of
Faceted Search & Find service v1.17_git39 as of Aug 09 2019


Alternative Linked Data Documents: PivotViewer | iSPARQL | ODE     Content Formats:       RDF       ODATA       Microdata      About   
This material is Open Knowledge   W3C Semantic Web Technology [RDF Data] Valid XHTML + RDFa
OpenLink Virtuoso version 07.20.3235 as of Sep 1 2020, on Linux (x86_64-generic-linux-glibc25), Single-Server Edition (61 GB total memory)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2020 OpenLink Software