CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC , it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA bus architecture, allowing reuse of existing SoC-components.
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| - Processor Local Bus (de)
- CoreConnect (en)
- Processor Local Bus (fr)
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| - Processor Local Bus (PLB) ist ein High-Speed Datenbus aus dem als CoreConnect bezeichneten Bus-System von IBM und wird bei PowerPC und verwandten Mikroprozessoren eingesetzt. Er stellt eine synchrone Standardschnittstelle zwischen Prozessorkernen und integrierten Bus-Controllern dar und verwendet je nach Anwendung separate 32-/64-/128-Bit breite Datenbusse. Der PLB wird im Rahmen des CoreConnect Bus-Systems vor allem in System on a Chip (SoC) eingesetzt. (de)
- Le Processor Local Bus (PLB) est un bus introduit[Quand ?] par IBM dans le cadre de l'architecture de bus , qui comprend également les bus OPB et DCR. Caractéristiques du bus PLB :
* Bus synchrone, non multiplexé
* Bus de lecture et d'écriture séparés
* Support de lecture/écriture concurrentes
* Multimaître à priorité programmable et disposant d'un arbitre
* Adresses sur 32 bits
* Implémentations sur 32, 64 et 128 bits de données
* Fréquences supportées : 66, 133 et 183 MHz (respectivement pour les versions 32, 64 et 128 bits)
* Pipeliné, support des interruptions de transfert
* Support des bursts de taille fixée et variable
* Support du verrou
* Portail de l’informatique (fr)
- CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC , it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA bus architecture, allowing reuse of existing SoC-components. (en)
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| - CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC , it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA bus architecture, allowing reuse of existing SoC-components. IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as Cadence, Ericsson, Lucent, Nokia, Siemens and Synopsys. The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their PowerPC 4x0 based designs. In the past, Xilinx was using CoreConnect as the infrastructure for all of their embedded processor designs. (en)
- Processor Local Bus (PLB) ist ein High-Speed Datenbus aus dem als CoreConnect bezeichneten Bus-System von IBM und wird bei PowerPC und verwandten Mikroprozessoren eingesetzt. Er stellt eine synchrone Standardschnittstelle zwischen Prozessorkernen und integrierten Bus-Controllern dar und verwendet je nach Anwendung separate 32-/64-/128-Bit breite Datenbusse. Der PLB wird im Rahmen des CoreConnect Bus-Systems vor allem in System on a Chip (SoC) eingesetzt. (de)
- Le Processor Local Bus (PLB) est un bus introduit[Quand ?] par IBM dans le cadre de l'architecture de bus , qui comprend également les bus OPB et DCR. Caractéristiques du bus PLB :
* Bus synchrone, non multiplexé
* Bus de lecture et d'écriture séparés
* Support de lecture/écriture concurrentes
* Multimaître à priorité programmable et disposant d'un arbitre
* Adresses sur 32 bits
* Implémentations sur 32, 64 et 128 bits de données
* Fréquences supportées : 66, 133 et 183 MHz (respectivement pour les versions 32, 64 et 128 bits)
* Pipeliné, support des interruptions de transfert
* Support des bursts de taille fixée et variable
* Support du verrou
* Portail de l’informatique (fr)
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